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1192 条记录 (耗时 0.025 秒)

    SUPERVISORY CONTROL OF POWER MANAGEMENT
    51.
    发明申请
    SUPERVISORY CONTROL OF POWER MANAGEMENT 有权

    公开(公告)号：US20220350394A1

    公开(公告)日：2022-11-03

    申请号：US17722289

    申请日：2022-04-15

    申请人： MICROSOFT TECHNOLOGY LICENSING, LLC

    发明人： Harish Srinivasan ,  Robert C. Combs

    IPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/3234 ,  G06F11/34 ,  G06F1/26 ,  G06F1/3209 ,  G06F11/30

    摘要： A supervisory control system provides power management in an electronic device by providing timeout periods for a hardware component to lower levels of the operating system such as a power management arbitrator and/or a hardware interface controller. The power management arbitrator and/or hardware interface controller transition at least a portion of a hardware component to a lower-power state based on monitored activity information of the hardware component. The supervisory control system may further provide wakeup periods to the power management arbitrator and/or a hardware interface controller to determine whether the hardware component should be transitioned to a higher-power state at the end of the wakeup period if the hardware component satisfies a transition condition.

    Memory system with region-specific memory access scheduling
    52.
    发明授权
    Memory system with region-specific memory access scheduling 有权

    公开(公告)号：US11474703B2

    公开(公告)日：2022-10-18

    申请号：US17199949

    申请日：2021-03-12

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Yi Xu ,  Nuwan S. Jayasena ,  Yuan Xie

    IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G06F13/42 ,  G06F1/3203 ,  G11C7/10

    摘要： An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

    Asymmetric energy efficient ethernet
    54.
    发明授权
    Asymmetric energy efficient ethernet 有权

    公开(公告)号：US11469920B2

    公开(公告)日：2022-10-11

    申请号：US17013410

    申请日：2020-09-04

    申请人： Marvell Asia Pte, Ltd.

    发明人： Saied Benyamin ,  Seid Alireza Razavi Majomard

    IPC分类号： G06F1/00 ,  H04L12/40 ,  G06F1/3203 ,  H04L12/02 ,  G06F1/26 ,  G06F1/3209

    摘要： An Ethernet transceiver is disclosed. The Ethernet transceiver includes transceiver circuitry to couple to one end of an Ethernet link. The transceiver circuitry includes transmit circuitry to transmit high-speed Ethernet data along the Ethernet link at a first data rate and receiver circuitry. The receiver circuitry includes adaptive filter circuitry and correlator circuitry. The receiver circuitry is responsive to an inline signal to operate in a low-power alert mode with the adaptive filter circuitry disabled and to receive alert signals from the Ethernet link simultaneous with transmission of the Ethernet data by the transmit circuitry. The alert signals are detected by the correlator circuitry and include a sequence of alert intervals exhibiting encoded data at a second data rate less than the first data rate.

    Selecting a low power state in an electronic device
    56.
    发明授权
    Selecting a low power state in an electronic device 有权

    公开(公告)号：US11467650B2

    公开(公告)日：2022-10-11

    申请号：US15819288

    申请日：2017-11-21

    申请人： Advanced Micro Devices, Inc.

    发明人： Alexander J. Branover

    IPC分类号： G06F1/3287 ,  G06F1/3296 ,  G06F1/3212 ,  G06F1/3206 ,  G06F1/3231 ,  G06F9/4401 ,  G06F1/3203 ,  G06F1/32

    摘要： The described embodiments include an electronic device that has a hardware controller and one or more hardware subsystems. The one or more hardware subsystems support an active state, a first low power state, and a second low power state. The first low power state and second low power states are separate low power states, with the first low power state being associated with a more rapid resumption of the active state than the second low power state. The hardware controller is configured to cause the one or more hardware subsystems to transition from the first low power state to the second low power state upon detecting an idle event that indicates that a user interaction is not likely to occur and to transition from the second low power state to the first low power state upon detecting an active event that indicates that a user interaction is likely to occur.

    Modular physical layer and integrated connector module for local area networks
    59.
    发明授权
    Modular physical layer and integrated connector module for local area networks 有权

    公开(公告)号：US11424953B2

    公开(公告)日：2022-08-23

    申请号：US16696850

    申请日：2019-11-26

    申请人： KinnexA, Inc.

    发明人： Ian Crayford ,  Kuan-Hsiung Wei ,  Shin-Hao Chien

    IPC分类号： G06F1/26 ,  H04L12/40 ,  H04L49/351 ,  G05F1/08 ,  H01R24/64 ,  H02J7/00 ,  H02M3/335 ,  H01L23/467 ,  H03K19/173 ,  G06F1/3203

    摘要： An Ethernet network is composed of one or more network infrastructure devices, such as a hubs, repeaters, switches or routers, which provides data interconnection and may provide operational power, or some part thereof, to remote network data terminal equipment such as a wireless access point, IP telephone, IP camera or network end station. Most Ethernet networks operate over a combination of the pairs in an unshielded twisted pair (UTP) or shielded twisted pair (STP) cable, or in some cases may operate over fiber optic cables. The individual links of Ethernet network, between the network infrastructure device and the Data Terminal Equipment (DTE) may be able to operate at one or more data rates such as 10 Mb/s, 100 Mb/s, 1 Gb/s, 2.5 Gb/s, 5 Gb/s and 10 Gb/s, or any combination thereof. The invention discloses an Ethernet Physical Layer (PHY) circuit, in combination with an Integrated Connector Module (ICM), which may reside inside the network equipment at either end of the Ethernet link. The combined PHY-ICM physical layer network device provides the appropriate encoding/decoding and signaling to operate over the specific network cable medium at the required data rate(s). The electrical and mechanical design of the combined PHY-ICM enables a modular approach such that during final assembly, the PHY-ICM can be optimized for operation over the appropriate data rate(s), whether it supports the provision of operational power between the network equipment, and if so at what power level, as well as other functionality. Furthermore, the PHY-ICM is designed to maintain a common electrical and mechanical footprint regardless of which of the features are included or excluded, to optimize the system cost for a specific maximum data rate, as well as minimize any re-engineering necessary on the part of the network equipment designer.

    Operating modes of a computer display
    60.
    发明授权
    Operating modes of a computer display 有权

    公开(公告)号：US11416053B2

    公开(公告)日：2022-08-16

    申请号：US17043228

    申请日：2018-07-31

    申请人： Hewlett-Packard Development Company, L.P.

    发明人： John W. Frederick ,  Greg Staten ,  Wen-Shih Chen

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/3218 ,  G09G5/00 ,  G06F1/3203

    摘要： An example power controller includes a comparator to compare an amount of power supplied at a port of a display device to a first power threshold corresponding to a first operating mode of the display device and a second power threshold corresponding to a second operating mode of the display device. The first power threshold is different from the second power threshold. The power controller further includes a mode controller to configure the display device to operate in at least one of the first operating mode or the second operating mode based on an output of the comparator.