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51.发明授权Continuous-time delta-sigma ADC for a radio receiver employing 200 kHz IF 有权采用200 kHz IF的无线电接收机的连续时间Δ-ΣADC公开(公告)号：US07242336B1
公开(公告)日：2007-07-10
申请号：US11369045
申请日：2006-03-06
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H03M3/00
摘要： A Continuous-Time Delta-Sigma Analog-to-Digital Converter (CTΔΣADC) for a radio frequency (RF) receiver employing a 200 kHz IF realizes an optimal signal-to-noise ratio using a programmable resonator that is set to resonate at 200 kHz. The programmable resonator is operably coupled to receive both an analog input signal at a low IF of 200 kHz and an analog feedback signal. From the analog input signal and the analog feedback signal, the programmable resonator produces a resonate signal at the low IF, and provides the resonate signal to a quantizer. The quantizer produces a digital output having a digital value coarsely reflecting an amplitude of the analog input signal. The CTΔΣADC further includes at least one programmable digital-to-analog converter (DAC) operably coupled to receive the digital output and to convert the digital output into the analog feedback signal provided to the programmable resonator.
摘要翻译： 采用200 kHz IF的射频（RF）接收机的连续时间Delta-Sigma模数转换器（CTDeltaSigmaADC）使用可设置为在200 kHz谐振的可编程谐振器实现最佳信噪比 。 可编程谐振器可操作地耦合以接收200kHz的低IF的模拟输入信号和模拟反馈信号。 从模拟输入信号和模拟反馈信号，可编程谐振器在低IF处产生谐振信号，并将谐振信号提供给量化器。 量化器产生具有粗略地反映模拟输入信号的幅度的数字值的数字输出。 CTDeltaSigmaADC还包括至少一个可编程数字 - 模拟转换器（DAC），可操作地耦合以接收数字输出并将数字输出转换为提供给可编程谐振器的模拟反馈信号。
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52.发明授权Configuration for digital-analog conversion of high-frequency digital input signal into carrier-frequency analog output signal 有权将高频数字输入信号数字模拟转换为载波频率模拟输出信号的配置公开(公告)号：US07132969B2
公开(公告)日：2006-11-07
申请号：US10525083
申请日：2003-07-28
申请人： Armin Fuchs , Björn Jelonnek , Gunter Wolff
发明人： Armin Fuchs , Björn Jelonnek , Gunter Wolff
IPC分类号： H03M1/66
摘要： A delay device has at least one first delay element and optional additional delay elements connected downstream from the first in a serially consecutive manner. The digital input signal is connected to an input of the first delay element and is connected to an input of a first D/A converter. The output of the first delay element is connected to an input of another D/A converter assigned thereto. The optional additional delay elements each have outputs connected to an input of another D/A converter assigned to the respective delay elements. All D/A converters are combined on the output side in a step-by-step manner so that output signals of all D/A converters form the analog output signal or the device. A specific coefficient is assigned to each D/A converter, and a specific delay time is assigned to each delay element for realizing a filter characteristic.
摘要翻译： 延迟装置具有至少一个第一延迟元件和以连续的连续方式从第一延迟元件连接到下游的可选附加延迟元件。 数字输入信号连接到第一延迟元件的输入，并连接到第一D / A转换器的输入。 第一延迟元件的输出连接到分配给其的另一个D / A转换器的输入端。 可选的附加延迟元件各自具有连接到分配给各个延迟元件的另一个D / A转换器的输入的输出。 所有D / A转换器以一步一步的方式在输出端组合，使得所有D / A转换器的输出信号形成模拟输出信号或器件。 特定系数被分配给每个D / A转换器，并且为每个延迟元件分配特定的延迟时间以实现滤波器特性。
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53.发明申请CONFIGURATION FOR DIGITAL-ANALOG CONVERSION OF HIGH-FREQUENCY DIGITAL INPUT SIGNAL INTO CARRIER-FREQUENCY ANALOG OUTPUT SIGNAL 有权高频数字输入信号数字模拟转换为载波频率模拟输出信号的配置公开(公告)号：US20060164275A1
公开(公告)日：2006-07-27
申请号：US10525083
申请日：2003-07-28
申请人： Armin Fuchs , Bjorn Jelonnek , Gunter Wolff
发明人： Armin Fuchs , Bjorn Jelonnek , Gunter Wolff
IPC分类号： H03M1/66
摘要： A delay device has at least one first delay element and optional additional delay elements connected downstream from the first in a serially consecutive manner. The digital input signal is connected to an input of the first delay element and is connected to an input of a first D/A converter. The output of the first delay element is connected to an input of another D/A converter assigned thereto. The optional additional delay elements each have outputs connected to an input of another D/A converter assigned to the respective delay elements. All D/A converters are combined on the output side in a step-by-step manner so that output signals of all D/A converters form the analog output signal or the device. A specific coefficient is assigned to each D/A converter, and a specific delay time is assigned to each delay element for realizing a filter characteristic.
摘要翻译： 延迟装置具有至少一个第一延迟元件和以连续的连续方式从第一延迟元件连接到下游的可选附加延迟元件。 数字输入信号连接到第一延迟元件的输入，并连接到第一D / A转换器的输入。 第一延迟元件的输出连接到分配给其的另一个D / A转换器的输入端。 可选的附加延迟元件各自具有连接到分配给各个延迟元件的另一个D / A转换器的输入的输出。 所有D / A转换器在输出端以一步一步的方式组合，使得所有D / A转换器的输出信号形成模拟输出信号或器件。 特定系数被分配给每个D / A转换器，并且为每个延迟元件分配特定的延迟时间以实现滤波器特性。
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公开(公告)号：US06897796B2
公开(公告)日：2005-05-24
申请号：US10888065
申请日：2004-07-09
申请人： Victor Dias , Josef Fenk
发明人： Victor Dias , Josef Fenk
摘要： The invention discloses a sigma-delta converter arrangement with a forward path including an amplifier and a quantizer with a clock input, and a feedback path with a D/A converter. The amplifier is coupled to an integrator which is in the form of a resonator with a tunable frequency and is actuated by a frequency synthesizer that also prescribes the clock rate of the quantizer. The synchronization between the quantizer and resonator results in highly accurate matching given inexpensive integratabiliy, which means that the sigma-delta converter is suitable for use in mobile radios, for example.
摘要翻译： 本发明公开了一种具有正向路径的Σ-Δ转换器装置，其包括具有时钟输入的放大器和量化器，以及具有D / A转换器的反馈路径。 该放大器耦合到具有可调谐频率的谐振器形式的积分器，并由也规定量化器的时钟速率的频率合成器启动。 量化器和谐振器之间的同步导致了高度精确的匹配，给出了廉价的可积分性，这意味着例如，Σ-Δ转换器适用于移动无线电。
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公开(公告)号：US20050030211A1
公开(公告)日：2005-02-10
申请号：US10888065
申请日：2004-07-09
申请人： Victor Dias , Josef Fenk
发明人： Victor Dias , Josef Fenk
摘要： The invention discloses a sigma-delta converter arrangement with a forward path including an amplifier and a quantizer with a clock input, and a feedback path with a D/A converter. The amplifier is coupled to an integrator which is in the form of a resonator with a tunable frequency and is actuated by a frequency synthesizer that also prescribes the clock rate of the quantizer. The synchronization between the quantizer and resonator results in highly accurate matching given inexpensive integratabiliy, which means that the sigma-delta converter is suitable for use in mobile radios, for example.
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公开(公告)号：US06842129B1
公开(公告)日：2005-01-11
申请号：US10691805
申请日：2003-10-22
申请人： Ian Robinson
发明人： Ian Robinson
摘要： Systems and methods are provided for providing feedback to a delta-sigma analog-to-digital converter assembly. A noise shaper preprocesses an analog input signal according to an analog feedback signal and an associated transfer function. A quantizer converts the preprocessed analog input signal into a digital output signal. A delta-sigma modulator shapes noise within a sample of the digital output signal. A digital-to-analog converter converts the shaped digital signal into an analog signal to provide the analog feedback signal.
摘要翻译： 提供的系统和方法用于向delta-sigma模数转换器组件提供反馈。 噪声整形器根据模拟反馈信号和相关的传递函数预处理模拟输入信号。 量化器将预处理的模拟输入信号转换为数字输出信号。 Δ-Σ调制器在数字输出信号的样本内整形噪声。 数模转换器将成形的数字信号转换为模拟信号以提供模拟反馈信号。
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公开(公告)号：US5736950A
公开(公告)日：1998-04-07
申请号：US384819
申请日：1995-01-31
IPC分类号： H03M3/02
CPC分类号： H03M3/396 , H03M7/3017 , H03M3/402 , H03M3/418 , H03M3/43 , H03M3/448 , H03M3/452 , H03M3/458 , H03M3/50 , H03M7/3028 , H03M7/3035 , H03M7/3037
摘要： A band-pass sigma-delta modulator includes a translator for tuning to a selected signal passband within the tuning range of the modulator. In a network implementation, the translator is integral with each integrator associated with the sigma-delta modulator(s). The translator can comprise a network having a transfer function defined in the Z-domain as (Z.alpha.-1)/(Z-.alpha.), where -1.ltoreq..alpha..ltoreq.1 defines the tuning. The value of .alpha. is defined as .alpha..tbd.cos(2.pi.f.sub.gm /f.sub.s), where f.sub.gm is the geometric mean frequency of the passband and f.sub.s is the input sample frequency of the sigma-delta modulator(s). The invention can benefit many signal processing applications such as, for example, A/D, D/A and D/D converters; and digital communication systems including digital radio and digital TV. In digital communications (e.g., radio, TV, etc.), the invention can be used where it is desirable to digitize the full tuning range or bandwidth of a receiver at an intermediate frequency early in the processing chain, thus allowing digital tuning or mixing of the desired signal. Such digital mixing or tuning overcomes the limitations of analog mixers/receivers, for example limited linearity in dynamic range as well as the problems associated with aliasing, artifacts, ghosts, harmonics, distortion, gain and phase mismatch, etc. The sigma-delta modulator of the invention also provides variable bandwidth, is operationally stable and is easily and inexpensively realized.
摘要翻译： 带通Σ-Δ调制器包括用于调谐到调制器的调谐范围内的选定信号通带的转换器。 在网络实现中，转换器与与Σ-Δ调制器相关联的每个积分器是一体的。 翻译器可以包括具有在Z域中定义的传递函数的网络（Zα1）/（Z-α），其中-1
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