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公开(公告)号：US20150102841A1
公开(公告)日：2015-04-16
申请号：US14516947
申请日：2014-10-17
发明人： Joseph M. Khayat , Marie Denison
IPC分类号： H03K17/08
CPC分类号： H03K17/08 , H03K2217/0027
摘要： An integrated circuit including a high-voltage n-channel MOS power transistor, a high-voltage n-channel MOS blocking transistor, a high-voltage n-channel MOS reference transistor, and a voltage comparator, configured to provide an overcurrent signal if drain current through the power transistor in the on state exceeds a predetermined value. The power transistor source node is grounded. The blocking transistor drain node is connected to the power transistor drain node. The blocking transistor source node is coupled to the comparator non-inverting input. The reference transistor drain node is fed by a current source and is connected to the comparator inverting input. The reference transistor gate node is coupled to a gate node of the power transistor. The comparator output provides the overcurrent signal. A process of operating the integrated circuit is disclosed.
摘要翻译： 包括高电压n沟道MOS功率晶体管，高压n沟道MOS截止晶体管，高压n沟道MOS参考晶体管和电压比较器的集成电路，被配置为在漏极 通过处于导通状态的功率晶体管的电流超过预定值。 功率晶体管源节点接地。 阻塞晶体管漏极节点连接到功率晶体管漏极节点。 阻塞晶体管源节点耦合到比较器同相输入。 参考晶体管漏极节点由电流源馈送并连接到比较器反相输入。 参考晶体管栅极节点耦合到功率晶体管的栅极节点。 比较器输出提供过电流信号。 公开了一种操作该集成电路的过程。
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公开(公告)号：US08749024B2
公开(公告)日：2014-06-10
申请号：US14073611
申请日：2013-11-06
发明人： Sameer Pendharkar , Marie Denison , Yongxi Zhang
IPC分类号： H01L27/082
CPC分类号： H01L27/082 , H01L21/8222 , H01L27/0259 , H01L27/0823 , H01L29/735
摘要： An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.
摘要翻译： 公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。 每个双极晶体管包括击穿诱导特征。 击穿诱发特征相对于彼此具有反射对称性。 还公开了一种用于形成集成电路的方法，该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。
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公开(公告)号：US20140061859A1
公开(公告)日：2014-03-06
申请号：US14073611
申请日：2013-11-06
发明人： Sameer Pendharkar , Marie Denison , Yongxi Zhang
IPC分类号： H01L27/082
CPC分类号： H01L27/082 , H01L21/8222 , H01L27/0259 , H01L27/0823 , H01L29/735
摘要： An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.
摘要翻译： 公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。 每个双极晶体管包括击穿诱导特征。 击穿诱发特征相对于彼此具有反射对称性。 还公开了一种用于形成集成电路的方法，该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。
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公开(公告)号：US20130307375A1
公开(公告)日：2013-11-21
申请号：US13946144
申请日：2013-07-19
IPC分类号： H01L41/08
CPC分类号： H01L41/08 , H01L27/20 , H01L41/0533 , H01L41/1134 , H01L41/1136 , H01L41/1138 , H01L41/22 , H01L41/318 , H01L2224/18
摘要： A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.
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