公开(公告)号：US11342326B2

公开(公告)日：2022-05-24

申请号：US16944025

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L23/535

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

公开(公告)号：US11329043B2

公开(公告)日：2022-05-10

申请号：US16823792

申请日：2020-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Wang ,  Min Cao ,  Shang-Wen Chang

IPC: H01L29/423 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first fin projecting vertically from a semiconductor substrate. A second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. A nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. A pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. A pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.

公开(公告)号：US11127631B2

公开(公告)日：2021-09-21

申请号：US16149597

申请日：2018-10-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L23/528 ,  H01L23/535 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/768

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a first conductive via electrically connected to the first epitaxial structure through a conductive contact. The first conductive via is misaligned with the first epitaxial structure. The semiconductor device structure further includes a second conductive via electrically connected to the second epitaxial structure. The second conductive via is aligned with the second epitaxial structure.

公开(公告)号：US11063041B2

公开(公告)日：2021-07-13

申请号：US16583438

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L23/50

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.