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公开(公告)号：US09915682B2
公开(公告)日：2018-03-13
申请号：US14841775
申请日：2015-09-01
CPC分类号： G01R1/06794 , G01R1/0408 , G01R1/06744 , G01R1/06755 , G01R31/2887 , G01R31/2893
摘要： A structure and method of facilitating testing of an electronic device (device under test or DUT) using a non-permanent and reusable structure to terminate contact pads and contact pin holes on a surface of the DUT.
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公开(公告)号：US09702906B2
公开(公告)日：2017-07-11
申请号：US14751792
申请日：2015-06-26
CPC分类号： G01R1/06794 , G01R1/0408 , G01R1/06744 , G01R1/06755 , G01R31/2887 , G01R31/2893
摘要： A structure and method of facilitating testing of an electronic device (device under test or DUT) using a non-permanent and reusable structure to terminate contact pads and contact pin holes on a surface of the DUT.
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公开(公告)号：US20170062960A1
公开(公告)日：2017-03-02
申请号：US15248652
申请日：2016-08-26
CPC分类号： H01R12/737 , H01R12/526 , H01R12/7076 , H01R43/205 , H05K1/024 , H05K1/0243 , H05K1/112 , H05K1/113 , H05K1/141 , H05K2201/094 , H05K2201/10159
摘要： A dual in-line memory module (DIMM) connector system is provided. The DIMM connector system includes a motherboard, a DIMM card and a connector by which the DIMM card is coupled with the motherboard. The motherboard includes a printed circuit board (PCB) formed of a mid-loss dielectric constant material, signal pads that are thinner than ground pads, ground pads disposed proximate to signal pads, signal vias connected to distal edges of signal pads and shared antipads. The DIMM card includes a printed circuit board (PCB) formed of a mid-loss dielectric constant material, signal pads that are thinner than ground pads, signal vias connected to distal edges of signal pads and shared antipads for respective pairs of signal vias.
摘要翻译： 提供双列直插式内存模块（DIMM）连接器系统。 DIMM连接器系统包括主板，DIMM卡和DIMM卡与主板耦合的连接器。 主板包括由中间损耗介电常数材料形成的印刷电路板（PCB），比接地焊盘更薄的信号焊盘，靠近信号焊盘设置的接地焊盘，连接到信号焊盘的远端边缘的信号通孔和共享的反焊盘。 DIMM卡包括由中间损耗介电常数材料形成的印刷电路板（PCB），比接地焊盘薄的信号焊盘，连接到信号焊盘的远端边缘的信号通孔和用于相应的信号通道对的共用反接头。
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公开(公告)号：US09548551B1
公开(公告)日：2017-01-17
申请号：US14833729
申请日：2015-08-24
CPC分类号： H01R12/737 , H01R12/526 , H01R12/7076 , H01R43/205 , H05K1/024 , H05K1/0243 , H05K1/112 , H05K1/113 , H05K1/141 , H05K2201/094 , H05K2201/10159
摘要： A dual in-line memory module (DIMM) connector system is provided. The DIMM connector system includes a motherboard, a DIMM card and a connector by which the DIMM card is coupled with the motherboard. The motherboard includes a printed circuit board (PCB) formed of a mid-loss dielectric constant material, signal pads that are thinner than ground pads, ground pads disposed proximate to signal pads, signal vias connected to distal edges of signal pads and shared antipads. The DIMM card includes a printed circuit board (PCB) formed of a mid-loss dielectric constant material, signal pads that are thinner than ground pads, signal vias connected to distal edges of signal pads and shared antipads for respective pairs of signal vias.
摘要翻译： 提供双列直插式内存模块（DIMM）连接器系统。 DIMM连接器系统包括主板，DIMM卡和DIMM卡与主板耦合的连接器。 主板包括由中间损耗介电常数材料形成的印刷电路板（PCB），比接地焊盘更薄的信号焊盘，靠近信号焊盘设置的接地焊盘，连接到信号焊盘的远端边缘的信号通孔和共享的反焊盘。 DIMM卡包括由中间损耗介电常数材料形成的印刷电路板（PCB），比接地焊盘薄的信号焊盘，连接到信号焊盘的远端边缘的信号通孔和用于相应的信号通道对的共用反接头。
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公开(公告)号：US20160371417A1
公开(公告)日：2016-12-22
申请号：US14842862
申请日：2015-09-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout that includes via groups in a two-to-one signal-to-ground via ratio configuration. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias.
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公开(公告)号：US20160371416A1
公开(公告)日：2016-12-22
申请号：US14745964
申请日：2015-06-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout that includes via groups in a two-to-one signal-to-ground via ratio configuration. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias.
摘要翻译： 一个方面是一种方法，其包括基于设计文件来识别多层电路板的信号通路的基本上均匀的分布，所述设计文件定义了包括二对一的信号对地通孔配置中的通孔组的布局。 通过间距的信号被确定为相邻的一对信号通孔之间的中心到中心距离。 将信号经由间距与目标最小钻孔距离进行比较。 在邻近的信号通孔对之间识别接地通孔。 基于确定相邻对的信号经由间距小于目标最小钻孔距离，至少一个信号通孔被定位成更靠近地面，使得在定位之后，相邻对的信号经由间距与 超过目标最小钻孔距离。 修改设计文件以包括信号通孔的定位。
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公开(公告)号：US20160124902A1
公开(公告)日：2016-05-05
申请号：US14529988
申请日：2014-10-31
发明人： Michael A. Cracraft
CPC分类号： G06F17/5009 , G06N3/006
摘要： Embodiments of the inventive subject matter include determining a plurality of potential full resolution locations for a particle representation for a second iteration of a particle swarm optimization, wherein the particle representation is associated with both a first full resolution location and a first reduced resolution location for a first iteration of the particle swarm optimization that has not yet completed and the second iteration is later than the first iteration. Embodiments further include determining that the plurality of full resolution locations reduces to a second reduced resolution location for the second iteration. Embodiments further include submitting the second reduced resolution location for fitness calculation prior to the first iteration completing.
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