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51.发明授权公开(公告)号：US10581029B2
公开(公告)日：2020-03-03
申请号：US15802431
申请日：2017-11-02
Inventor： Jun Wang , Ce Zhao , Dongfang Wang , Bin Zhou
Abstract: The present disclosure provides a method for manufacturing an organic electroluminescence device, including steps of: adjusting a grating period of a periodic grating structure in such a manner that a wavelength of an emergent light beam caused by SP-coupling is within a predetermined range of a light-emission peak of the organic electroluminescence device; and forming the periodic grating structure in the organic electroluminescence device in accordance with the obtained grating period by adjustment.
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公开(公告)号：US10578484B2
公开(公告)日：2020-03-03
申请号：US15512868
申请日：2016-05-13
Inventor： Tuan Liang , Zhaolei Li , Shuanghui Zhao , Yuan Liu , Yubing Zhang , Gang Luo , Jun Wang , Yi Qu
Abstract: The present disclosure provides a backlight source monitoring device and a pattern generator. The backlight source monitoring device includes a base, a fixing structure arranged on the base and configured to fix a backlight source to be monitored, a monitoring element fixed on the base and configured to monitor a brightness value of the backlight source to obtain brightness data, and a display element connected with the monitoring element and configured to receive and display the brightness data obtained by the monitoring element.
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53.发明授权公开(公告)号：US10403209B2
公开(公告)日：2019-09-03
申请号：US15244830
申请日：2016-08-23
Inventor： Jun Wang , Xinxin Jin , Yi Qu , Yi Zhang , Tianyi Cheng
IPC: G09G3/3266 , G09G3/3291 , G09G3/3258 , H01L27/32 , H01L51/00 , G09G3/3233
Abstract: An array substrate, an electrical aging method, a display device and a manufacturing method thereof. The array substrate includes: pixel circuits disposed in a display area, where each of the pixel circuits is disposed in a corresponding pixel region of the display area; a scanning drive circuit disposed outside the display area; a plurality of scanning-line groups for connecting the pixel circuits to the scanning drive circuit; a voltage input interface disposed outside the display area; and a wire group for connecting the plurality of scanning-line groups to the voltage input interface. An insulating layer is disposed between the wire group and the scanning drive circuit.
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公开(公告)号：US10276603B2
公开(公告)日：2019-04-30
申请号：US15567193
申请日：2016-10-14
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
IPC: H01L27/12 , G02F1/1362 , H01L21/66
Abstract: The present application discloses an array substrate including a first signal line layer having a plurality of rows of first signal lines; a second signal line layer having a plurality of columns of second signal lines; the plurality of rows of first signal lines crossing over the plurality of columns of second signal lines defining a plurality of subpixels; a first insulating layer and a second insulating layer between the first signal line layer and the second signal line layer; the first insulating layer on a side of the second insulating layer proximal to the first signal line layer; a repair line between the first insulating layer and the second insulating layer, the repair line corresponding to one of the plurality of columns of second signal lines; and a first via and a second via extending through the second insulating layer; the repair line being electrically connected to the corresponding one of the plurality of columns of second signal lines through the first via and the second via, respectively.
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公开(公告)号：US10090831B2
公开(公告)日：2018-10-02
申请号：US15122389
申请日：2015-04-09
Inventor： Jun Wang , Xinxin Jin , Liang Sun , Yuebai Han , Guoqing Zhang
IPC: G09G3/3233 , H03K17/16
Abstract: The present disclosure relates to a method of electrically aging a PMOS thin film transistor. The method includes applying a first voltage Vg with an amplitude of A volts to a gate of the PMOS thin film transistor; applying a second voltage Vs with an amplitude of (A−40) to (A−8) volts to a source of the PMOS thin film transistor; and applying a third voltage Vd with an amplitude of (A−80) to (A−16) volts to a drain of the PMOS thin film transistor. Application of the first voltage Vg, the second voltage Vs and the third voltage Vd is maintained for a predetermined time period, and Vd−Vs
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Patent Agency Ranking
公开(公告)号：US11837665B2
公开(公告)日：2023-12-05
申请号：US17806578
申请日：2022-06-13
Inventor： Jun Wang , Zhonghao Huang , Yongliang Zhao , Seung Moo Rim
IPC: H01L29/786 , H01L27/12 , H01L29/49 , H01L29/66 , G02F1/1368 , H10K59/121
CPC classification number: H01L29/78678 , H01L27/127 , H01L27/1222 , H01L29/4908 , H01L29/66765 , H01L29/78696 , G02F1/1368 , H10K59/1213
Abstract: A thin film transistor includes a substrate, and a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode which are on the substrate. The active layer includes a channel region between the source electrode and the drain electrode and the channel region includes an edge region along a channel length direction and a main region outside the edge region. The thin film transistor further includes an auxiliary layer, a projection of the auxiliary layer on the substrate is at least partially overlapped with a projection of the edge region of the channel region on the substrate, and the auxiliary layer is configured to enhance a turn-on voltage of the edge region of the channel region.
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公开(公告)号：US11804494B2
公开(公告)日：2023-10-31
申请号：US17349164
申请日：2021-06-16
Inventor： Haitao Wang , Jun Cheng , Ming Wang , Qinghe Wang , Jun Wang , Tongshang Su
CPC classification number: H01L27/124 , H01L27/0266 , H01L27/0288 , H01L27/127 , H01L27/1237 , H01L27/1255
Abstract: The disclosure discloses an array substrate and a preparation method thereof, a display panel and a display device. The array substrate includes: a substrate, and a first metal layer, a metal oxide layer and a second metal layer which are sequentially stacked and isolated from each other on the substrate; the first metal layer includes a light shading metal, a first electrode, and an anti-static line; the metal oxide layer includes a first active layer; the second metal layer includes a gate line and a second electrode; the gate line is connected with the anti-static line through a first TFT, one of the first electrode and the second electrode forms the source and drain electrodes of the first TFT, and the other forms the gate electrode of the first TFT; and the source is electrically connected with the gate line, and the drain is electrically connected with the anti-static line.
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公开(公告)号：US11675237B2
公开(公告)日：2023-06-13
申请号：US17241140
申请日：2021-04-27
Inventor： Maokun Tian , Zhonghao Huang , Xu Wu , Chengjun Qi , Jun Wang , Dan Liu
IPC: G02F1/1362 , H01L27/12
CPC classification number: G02F1/136209 , H01L27/127 , H01L27/1237
Abstract: An array substrate includes a base substrate, a light-shielding pattern, a buffer pattern, an active layer, a gate insulating layer and a first passivation layer provided with a first via, a second via and a third via, and a source and a drain. An entire orthographic projection of the active layer on the base substrate coincides with an orthographic projection of at least part of the buffer pattern on the base substrate. The orthographic projection of the buffer pattern on the base substrate is within a border of an orthographic projection of the light-shielding pattern on the base substrate, and its area is less than an area of the orthographic projection of the light-shielding pattern on the base substrate. One of the source and the drain is coupled to the active layer through the first via, and another one is coupled to the active layer through the second via and the light-shielding pattern through the third via.
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公开(公告)号：US11563071B2
公开(公告)日：2023-01-24
申请号：US16617962
申请日：2019-03-18
Inventor： Jun Wang , Zhantao Wang , Runmin Tang , Qiancheng Zhao , Xing Ren
Abstract: A display panel, methods for manufacturing and detecting the display panel and a display device are provided. The display panel includes: a substrate, including a display region and a circuit region; multiple signal line terminals in the circuit region, coupled with signal lines respectively; multiple switch elements in the circuit region, first terminals of the switch elements are coupled with the signal line terminals respectively; multiple leads located in the circuit region and on a side of the signal line terminals distal to the display region, spaced apart from each other along a first direction, extending along a second direction, first ends of the leads are coupled with the second terminals of the switch elements respectively, second ends of the leads in the second direction extend to an edge of the substrate, each switch element is configured to connect or disconnect the first terminal and the second terminal thereof.
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公开(公告)号：US11527599B2
公开(公告)日：2022-12-13
申请号：US16665410
申请日：2019-10-28
Inventor： Haitao Wang , Qinghe Wang , Jun Wang , Guangyao Li , Yang Zhang , Jun Liu , Dongfang Wang
IPC: H01L27/32 , G02F1/1362
Abstract: Disclosed are an array substrate, a method for fabricating the same, a display panel, and a display device, and the array substrate includes: an underlying substrate, and gate lines and data lines located on the underlying substrate, and intersecting with each other, a layer where the gate lines are located is between a layer where the data lines are located, and the underlying substrate; and the array substrate further includes a buffer layer located between the underlying substrate and the layer where the gate lines are located; and the buffer layer includes a plurality of through-holes, where orthographical projections of the through-holes onto the underlying substrate cover orthographical projections of the areas where the gate lines intersect with the data lines, onto the underlying substrate.
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