公开(公告)号：US10521232B2

公开(公告)日：2019-12-31

申请号：US15431955

申请日：2017-02-14

Applicant: ARM Limited

Inventor： David James Seal ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/76

Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.

公开(公告)号：US10241933B2

公开(公告)日：2019-03-26

申请号：US15123805

申请日：2015-03-04

Applicant: ARM LIMITED

Inventor： Matthew James Horsnell ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC: G06F12/14 ,  G06F9/46

Abstract: An asymmetric multiprocessor system includes a plurality of processor cores supporting transactional memory via controllers as well as one or more processor cores which do not support transactional memory via hardware. The controllers respond to receipt of a request for exclusive access to a lock address by determining whether or not their associated processors is currently executing a memory transaction guarded by a lock value stored at that lock address and if their processor is executing such a transaction, then delaying releasing the lock address for exclusive access until a predetermined condition is met. If the processor is not executing such a guarded memory transaction, then the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and/or that the request has previously been received and refused a threshold number of times. The request may arise through execution of a transaction start instruction which serves to read a lock address from an architectural register storing the lock address should the processor executing that transaction start instruction not already be executing a pending memory transaction. If the processor is already executing a memory transaction, then the transaction start instruction need not access the lock value stored at the lock address held within the lock address register as it may be assumed that the lock value has already been checked.

公开(公告)号：US09213828B2

公开(公告)日：2015-12-15

申请号：US13680352

申请日：2012-11-19

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite ,  Simon John Craske

IPC: G06F21/00 ,  G06F21/52 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F21/52 ,  G06F9/30134 ,  G06F9/462 ,  G06F2221/034 ,  G06F2221/2105

Abstract: A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call.

Abstract translation: 数据处理装置包括处理电路和数据存储器，其包括包括安全区域和较不安全区域的多个区域。 安全区域被配置为存储当在安全域中操作时电路可访问的敏感数据，并且当在较不安全的域中操作时不被电路访问。 数据存储器包括在安全区域中具有安全堆栈的多个堆叠。 堆栈访问电路被配置为将预定的处理状态存储到安全堆栈。 处理电路还包括故障检查电路，其被配置为如果存储在预定相对位置中的数据是第一值，则识别第一故障状况。 这提供了防止来自较不安全的域的攻击的保护，例如执行从异常返回的函数调用或来自函数调用的异常返回。

公开(公告)号：US09201749B2

公开(公告)日：2015-12-01

申请号：US14448038

申请日：2014-07-31

Applicant: ARM Limited

Inventor： Michael John Williams ,  Richard Roy Grisenthwaite

IPC: G06F11/00 ,  G06F11/22 ,  G06F11/36

CPC classification number: G06F11/2236 ,  G06F11/3632

Abstract: A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception.

Abstract translation: 一种用于控制处理器以单步模式执行使得来自指令流的单个指令被执行的方法和装置，处理器确定单个指令是否是至少一种预定类型的指令中的一种，并将类型指示器存储在 在处理器处理单个指令之后，采集数据存储位置和诊断异常。 此外，执行诊断操作，包括访问存储在数据存储位置中的类型指示符，并且当单个指令不是预定类型中的一个时，控制处理器以单步模式继续执行指令，并且当单个指令 指令是至少一种预定类型之一，控制处理器退出单步模式，并且不执行指令流内的下一条指令作为跟随异常的单个指令。

公开(公告)号：US09104425B2

公开(公告)日：2015-08-11

申请号：US14149141

申请日：2014-01-07

Applicant: ARM LIMITED

Inventor： Richard Roy Grisenthwaite

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30101 ,  G06F9/30189

Abstract: Processing circuitry 4 has a plurality of exception states EL0-EL3 for handling exception events, the exception states including a base level exception state EL0 and at least one further level exception state EL1-EL3. Each exception state has a corresponding stack pointer indicating the location within the memory of a corresponding stack data store 35. When the processing circuitry is in the base level exception state EL0, stack pointer selection circuitry 40 selects the base level stack pointer as a current stack pointer indicating a current stack data store for use by the processing circuitry 4. When the processing circuitry 4 is a further exception state, the stack pointer selection circuitry 40 selects either the base level stack pointer or the further level stack pointer corresponding to the current further level exception state as a current stack pointer.

Abstract translation: 处理电路4具有用于处理异常事件的多个异常状态EL0-EL3，异常状态包括基本电平异常状态EL0和至少一个进一步的电平异常状态EL1-EL3。 每个异常状态具有指示相应堆栈数据存储器35的存储器内的位置的相应堆栈指针。当处理电路处于基本电平异常状态EL0时，堆栈指针选择电路40选择基本电平堆栈指针作为当前堆栈 指示当前堆栈数据存储供处理电路4使用。当处理电路4是另外的异常状态时，堆栈指针选择电路40选择对应于当前进一步的基本级堆栈指针或进一步的级堆栈指针 级异常状态作为当前堆栈指针。

公开(公告)号：US20130212700A1

公开(公告)日：2013-08-15

申请号：US13741709

申请日：2013-01-15

Applicant: ARM Limited

Inventor： Thomas Christopher GROCUTT ,  Richard Roy Grisenthwaite

IPC: G06F21/60

CPC classification number: G06F21/606 ,  G06F9/3009 ,  G06F9/30101 ,  G06F21/52 ,  G06F21/74 ,  G06F2209/481 ,  G06F2221/2105

Abstract: A data processing apparatus and method are provided for handling exceptions, including processing circuitry configured to perform data processing operations in response to program code, said circuitry including exception control circuitry. A plurality of registers are provided including a first and second subsets of registers, and a data store. The data store includes a secure region and a less secure region, wherein the secure region is for storing data accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain. The exception control circuitry performs state saving of data from the first subset of registers before triggering the processing circuitry to perform an exception handling routine corresponding to the exception. Where background processing was performed by the processing circuitry in the secure domain, the exception control circuitry performs additional state saving of the data.

Abstract translation: 提供了一种用于处理异常的数据处理装置和方法，包括配置为响应于程序代码执行数据处理操作的处理电路，所述电路包括异常控制电路。 提供了多个寄存器，包括第一和第二寄存器子集，以及数据存储器。 数据存储器包括安全区域和较不安全的区域，其中安全区域用于存储当在安全域中操作时由处理电路可访问的数据，并且当在较不安全的域中操作时由处理电路不可访问。 异常控制电路在触发处理电路之前对寄存器的第一子集进行数据的状态保存，以执行与异常相对应的异常处理程序。 在由安全域中的处理电路执行背景处理的情况下，异常控制电路执行数据的附加状态保存。

公开(公告)号：US20130205413A1

公开(公告)日：2013-08-08

申请号：US13735350

申请日：2013-01-07

Applicant: ARM Limited

Inventor： Thomas Christopher GROCUTT ,  Richard Roy Grisenthwaite

IPC: G06F21/64

CPC classification number: G06F21/64 ,  G06F9/30134 ,  G06F9/462 ,  G06F21/52 ,  G06F2221/2105

Abstract: A data processing apparatus 2 has processing circuitry 4 which has a secure domain and a less secure domain of operation. When operating in the secure domain the processing circuitry 4 has access to data that is not accessible in the less secure domain. In response to a control flow altering instruction, processing switches to a program instruction at a target address. Domain selection is performed to determine a selected domain in which the processing circuitry 4 is to operate for the instruction at the target address. Domain checking can be performed to check which domains are allowed to be the selected domain determining the domain selection. A domain check error is triggered if the selected domain in the domain selection is not an allowed selected domain.

Abstract translation: 数据处理装置2具有处理电路4，其具有安全域和较不安全的操作域。 当在安全域中操作时，处理电路4可以访问在较不安全的域中不可访问的数据。 响应于控制流改变指令，处理切换到目标地址处的程序指令。 执行域选择以确定处理电路4将在目标地址处的指令操作的所选域。 可以执行域检查以检查哪些域被允许是确定域选择的所选域。 如果域选择中的选定域不是允许的选定域，则会触发域检查错误。