公开(公告)号：US20210390360A1

公开(公告)日：2021-12-16

申请号：US16898085

申请日：2020-06-10

Applicant: Arm Limited

Inventor： James Edward Myers ,  Ludmila Cherkasova ,  Parameshwarappa Anand Kumar Savanth ,  Sahan Sajeewa Hiniduma Udugama Gamage ,  Mbou Eyole

IPC: G06K19/07

Abstract: Disclosed are methods, systems and devices for varying operations of a transponder device based, at least in part, on an availability of energy and/or power that may be harvested and/or collected. In one particular implementation, operations to generate one or more signals from sensor circuitry and/or to perform computations may be varied based, at least in part, on an availability of harvestable and/or collectable energy and/or power.

公开(公告)号：US11194581B2

公开(公告)日：2021-12-07

申请号：US16658494

申请日：2019-10-21

Applicant: Arm Limited

Inventor： Mbou Eyole

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: Data processing apparatuses, methods of data processing, instructions, and simulator computer programs for providing a corresponding instruction execution environment are disclosed. Decode circuitry is responsive to an instance of a predetermined instruction type to cause issue circuitry to issue at least one subsequent instruction for execution to one of first and second instruction execution circuitry which support decoupled access-execute instruction execution. The predetermined instruction type is thus a steering instruction for at least one subsequent instruction and the programmer is provided with a mechanism for determining which program instructions are treated as access instructions and which are treated as execute instructions.

公开(公告)号：US11132196B2

公开(公告)日：2021-09-28

申请号：US16090357

申请日：2017-04-06

Applicant: ARM Limited

Inventor： Mbou Eyole ,  Jacob Eapen ,  Alejandro Martinez Vicente

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38

Abstract: Address collisions are managed when performing vector operations. A register store stores vector operands. Execution circuitry performs memory access operations to move the vector operands between the register store and memory and data processing operations using the vector operands. The execution circuitry may iteratively execute a vector loop, where during each iteration the execution circuitry executes a sequence of instructions to implement the vector loop. The sequence includes a check instruction identifying a plurality of memory addresses. The execution circuitry responds to the check instruction to determine whether an address hazard condition exists among the plurality of memory addresses. For each iteration of the vector loop, the execution circuitry responds to the check instruction determining an absence of the hazard address condition to employ a default level of vectorization when executing the sequence of instructions to implement the vector loop. But in the presence of the address hazard condition, the execution circuitry employs a reduced level of vectorization to implement the vector loop.

公开(公告)号：US11113164B2

公开(公告)日：2021-09-07

申请号：US16641387

申请日：2018-08-30

Applicant: ARM Limited

Inventor： Balaji Venu ,  Matthias Lothar Boettcher ,  Mbou Eyole

IPC: G06F11/22 ,  G06F9/30 ,  G06F9/46 ,  G06F11/07 ,  G06F11/10 ,  G06F11/16 ,  G06F11/18 ,  G11C7/10

Abstract: A buffer (72), (74), (76), (60), (78), (20), (82-90) has a number of entries for buffering items associated with data processing operations. Buffer control circuitry (100) has a redundant allocation mode in which, on allocating a given item to the buffer, the item is allocated to two or more redundant entries of the buffer. On reading or draining an item from the buffer, the redundant entries are compared and an error handling response is triggered if a mismatch is detected. By effectively reducing the buffer capacity, this simplifies testing for faults in buffer entries.

公开(公告)号：US11042378B2

公开(公告)日：2021-06-22

申请号：US15743735

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Mbou Eyole ,  Alejandro Martinez Vicente

IPC: G06F9/30 ,  G06F9/32

Abstract: Data processing apparatus comprises processing circuitry to selectively apply a vector processing operation to data items at positions within data vectors according to the states of a set of respective predicate flags associated with the positions, the data vectors having a data vector processing order, each data vector comprising a plurality of data items having a data item order, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a propagation instruction to control the instruction processing circuitry to derive a set of predicate flags applicable to a current data vector in dependence upon a set of predicate flags applicable to a preceding data vector in the data vector processing order, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are inactive, all of the derived predicate flags in the set applicable to the current data vector are inactive.

公开(公告)号：US09875214B2

公开(公告)日：2018-01-23

申请号：US14814590

申请日：2015-07-31

Applicant: ARM LIMITED ,  APPLE, INC.

Inventor： Mbou Eyole ,  Nigel John Stephens ,  Jeffry Gonion ,  Alex Klaiber ,  Charles Tucker

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F15/8076 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30192 ,  G06F9/345 ,  G06F9/3455 ,  G06F9/355 ,  G06F9/3887

Abstract: An apparatus and method are provided for transferring a plurality of data structures between memory and a plurality of vector registers, each vector register being arranged to store a vector operand comprising a plurality of data elements. Access circuitry is used to perform access operations to move data elements of vector operands between the data structures in memory and specified vector registers, each data structure comprising multiple data elements stored at contiguous addresses in the memory. Decode circuitry is responsive to a single access instruction identifying a plurality of vector registers and a plurality of data structures that are located discontiguously with respect to each other in the memory, to generate control signals to control the access circuitry to perform a sequence of access operations to move the plurality of data structures between the memory and the plurality of vector registers such that the vector operand in each vector register holds a corresponding data element from each of the plurality of data structures. This provides a very efficient mechanism for performing complex access operations, resulting in an increase in execution speed, and potential reductions in power consumption.