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公开(公告)号：US5457404A
公开(公告)日：1995-10-10
申请号：US118801
申请日：1993-09-08
IPC分类号： H03K3/353 , H03K19/00 , H03K19/017 , H03K19/177 , H03R17/09
CPC分类号： H03K19/0016 , H03K19/01721 , H03K19/01728
摘要： A zero-power wide OR gate for implementing the "sum" of the "sum of product terms" in a programmable logic device (PLD). The wide OR gate includes a single additional input transistor for each added "product term" input from a sense amplifier. The wide OR gate further includes circuitry to decouple the current supply from sense amplifiers turned on during sleep mode to limit power utilized. To increase operation speed, the wide OR gate utilizes a strong current source when sense amplifiers are all turned off to quickly pull up internal circuitry while utilizing a weak current source when sense amplifiers turn on to allow the sense amplifiers to more easily overcome the current supply. To further increase speed, the wide OR gate includes a threshold shifting transistor to shift the pull down threshold of the output inverter for when all sense amplifiers are turned off while shifting the threshold back for when a sense amplifier transitions to on.
摘要翻译： 用于在可编程逻辑器件（PLD）中实现“产品术语之和”的“和”的零功率宽或门。 宽或门包括一个单独的附加输入晶体管，用于从读出放大器输入的每个附加的“产品项”。 宽或门还包括电路，用于在睡眠模式期间将电流源与读出放大器导通，以限制使用的功率。 为了提高操作速度，当读出放大器全部关闭时，宽门或门将使用强电流源，以在读取放大器导通时使用弱电流源快速上拉内部电路，从而允许读出放大器更容易地克服当前电源 。 为了进一步提高速度，宽或门包括阈值移位晶体管，以移位输出反相器的下拉阈值，用于当所有读出放大器关闭时，同时在读出放大器转换为导通时向前移动阈值。
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公开(公告)号：US5410268A
公开(公告)日：1995-04-25
申请号：US118432
申请日：1993-09-08
IPC分类号： G11C17/00 , G11C7/06 , G11C16/06 , G11C17/18 , H03K3/356 , H03K19/00 , H03K19/177 , H03K5/12 , G01R19/00 , H03K5/153
CPC分类号： G11C7/067 , H03K19/0016 , H03K3/356052 , H03K3/356147
摘要： A zero-power sense amplifier for implementing a wide or multiple input NOR gate for receiving a product term of a group of array cells in a programmable logic device (PLD). In a sleep mode, or low power mode, the zero-power sense amplifier latches its previous state while drawing negligible power rather than returning to one particular state, such as a low state, as in previous devices, enabling recovery time to be reduced after entering an awake mode. The zero power sense amplifier further reduces recovery time upon powering up from a sleep mode by maintaining the product term voltage close to a threshold input voltage during sleep mode while still drawing negligible power.
摘要翻译： 一种用于实现宽输入或多输入NOR门的零功率读出放大器，用于接收可编程逻辑器件（PLD）中的一组阵列单元的乘积项。 在睡眠模式或低功率模式下，零功率读出放大器锁存其先前的状态，同时绘制可忽略的功率，而不是像以前的设备那样返回到诸如低状态的一个特定状态，使得恢复时间能够在之后降低 进入唤醒模式。 零功率读出放大器通过在睡眠模式期间保持产品项电压接近阈值输入电压同时仍然可以忽略不计的功率进一步减少从休眠模式上电时的恢复时间。
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公开(公告)号：US06720755B1
公开(公告)日：2004-04-13
申请号：US10146734
申请日：2002-05-16
IPC分类号： G05F316
CPC分类号： G05F3/30
摘要： A band gap reference includes circuitry providing a reference voltage (VDIODE) at 1.0 volt or below to provide a stable reference for 1.3 volt or lower circuits, which would otherwise not function accurately with a typical band gap reference of 1.2 volts. The band gap reference includes an op-amp equally driving the gate of various current source transistors. A first current source drives a BJT transistor connected in a diode fashion, while a second current source drives a further diode connected BJT transistor through a resistor. An output VDIODE is provided from a further resistor connected to two additional current sources. The first of these current sources is driven by the op-amp output to increase output with temperature, while the second of these current sources is driven by a replicating op-amp connected to a resistor providing current decreasing with temperature, both current sources functioning to provide a stable low voltage VDIODE on the resistor with variations in temperature and supply voltage.
摘要翻译： 带隙基准包括提供1.0伏特或更低电压的参考电压（VDIODE）的电路，为1.3伏特或更低电路提供稳定的参考电压，否则电压将不能用1.2伏的典型带隙基准精确地运行。 带隙基准包括一个均等地驱动各种电流源晶体管的栅极的运算放大器。 第一电流源驱动以二极管方式连接的BJT晶体管，而第二电流源通过电阻驱动另一个连接的BJT晶体管的二极管。 输出VDIODE由连接到两个附加电流源的另一电阻器提供。 这些电流源中的第一个由运算放大器输出驱动，以通过温度增加输出，而第二个电流源由连接到电阻器的复制运算放大器驱动，提供电流随温度的降低，两个电流源均起作用 在电阻上提供稳定的低电压VDIODE，温度和电源电压变化。
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公开(公告)号：US06714048B1
公开(公告)日：2004-03-30
申请号：US10146739
申请日：2002-05-16
IPC分类号： H03K190175
CPC分类号： H03K19/018585
摘要： An input/output buffer is provided with input buffer circuitry which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The input buffer portion includes a CMOS transistors for driving the output (OUT) between the VSS and VDD rails similar to CMOS logic. The voltage and current on the output of the input buffer as controlled by the CMOS transistors is clamped to levels depending on a mode select signal applied to selectively provide different output levels compatible with PCI, GTL, PECL, ECL and SSTI signals.
摘要翻译： 输入/输出缓冲器具有输入缓冲器电路，其可用于使集成电路选择性地与诸如PCI，GTL，PECL，ECL和SSTI之类的多种接口类型之一兼容。 输入缓冲器部分包括CMOS晶体管，用于驱动类似于CMOS逻辑的VSS和VDD电源之间的输出（OUT）。 由CMOS晶体管控制的输入缓冲器的输出上的电压和电流被钳位到取决于施加到选择性地提供与PCI，GTL，PECL，ECL和SSTI信号兼容的不同输出电平的模式选择信号的电平。
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55.发明授权公开(公告)号：US06714043B1
公开(公告)日：2004-03-30
申请号：US10147199
申请日：2002-05-16
IPC分类号： H03K19177
CPC分类号： H03K19/17744 , H03K19/018585 , H03K19/1778 , H03K19/17788
摘要： An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The output buffer portion has an input connected to an output signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). Control power switches driving the gates of multiple CMOS buffer transistors to provide sufficient current for rapid switching, and limit current after switching to prepare for a subsequent output transition. The CMOS buffer transistors are selectively enabled to control output drive current. Selectable pull-up and pull-down reference circuits provide references (VRFPU, VRFPPU, VRFPD and VRFPPD) to control the current of the buffer output during transition of the output, while maintaining the output voltage level at a desired voltage with minimal current level after transition.
摘要翻译： 输入/输出缓冲器具有输出缓冲器部分，其可用于使集成电路选择性地与诸如PCI，GTL，PECL，ECL和SSTI之类的接口类型之一兼容。 输出缓冲器部分具有连接到输出信号节点（D）的输入，其中集成电路上的组件提供用于在输出焊盘（PAD）处连接到外部电路的输出信号。 驱动多个CMOS缓冲晶体管的栅极的控制电源开关提供足够的电流用于快速开关，并且在切换之后限制电流以准备随后的输出转换。 选择性地使能CMOS缓冲晶体管来控制输出驱动电流。 可选择的上拉和下拉参考电路提供参考（VRFPU，VRFPPU，VRFPD和VRFPPD），用于在输出转换期间控制缓冲器输出的电流，同时将输出电压电平保持在最小电流水平的期望电压 过渡。
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56.发明授权Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources 有权用于配置具有可变粒度组件的FPGA以提供对互连资源的时间共享访问的方法公开(公告)号：US06590415B2
公开(公告)日：2003-07-08
申请号：US09841209
申请日：2001-04-23
IPC分类号： G06F738
CPC分类号： H03K19/17736 , H03K19/1737
摘要： A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.
摘要翻译： 可变格式架构（VGA）用于从原始构建元素（CBE）合成每个给定任务的适当量的动态复用能力。 这些可配置构建单元（CBE）的未使用的配置可重新配置以执行更多的逻辑功能来代替动态复用功能。每个CBE可以可编程配置为提供不超过2对1的动态多路复用器（2：1 DyMUX ）。 然后可以将这种合成的2:1 DyMUX的动态可选输出输出到共享互连线上。 CBE的对可以合成，以有效地定义4：1的DyMUX，每个这样的4：1多路复用器占用可配置的构建块（CBB）结构。 CBB的对可以合成组合，以有效地定义8：1 DyMUX，每个这样合成的8：1多路复用器占据L形VGB结构（可变颗粒块）的垂直或水平延伸的腿部分。 然后，VGB的如此配置的腿部分可以将由其8：1 DyMUX选择的信号输出到由VGB支路驱动的共享互连线上。 VGB的对或四重组可以合成组合，以有效地定义高阶N：1 DyMUX。
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57.发明授权Programmable optimized-distribution logic allocator for a high-density complex PLD 失效用于高密度复合PLD的可编程优化分配逻辑分配器公开(公告)号：US06531890B1
公开(公告)日：2003-03-11
申请号：US08459570
申请日：1995-06-02
IPC分类号： H03K19177
CPC分类号： H03K19/177 , H03K19/1737 , H03K19/17704
摘要： A programmable optimized-distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable optimized-distribution logic allocator provides an optimized number of product terms to each I/O pin of the CPLDS and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable optimized-distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product-term clusters, to a programmably selected logic macrocell. Specifically, the programmable optimized-distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an input terminal connected an input line in the plurality of input lines and an output terminal connected to an output line in the plurality of output lines.
摘要翻译： 可编程优化分配逻辑分配器增强了包括逻辑分配器在内的非常高密度CPLD的速度，硅利用率，逻辑效率，逻辑利用率和可扩展性。 可编程优化分配逻辑分配器为CPLDS的每个I / O引脚提供优化数量的产品术语，并且与反馈相同的统一数量的产品术语。 然而，没有产品术语永久连接到特定的宏单元或特定的I / O引脚。 可编程优化分配逻辑分配器包括多个路由器元件，其中每个路由器元件将选择数量的乘积项和项的总和从PAL结构（即选定数量的逻辑产品项集群）引导到 可编程选择逻辑宏单元。 具体地，可编程优化分配逻辑分配器具有多条输入线，多条输出线和多条可编程路由器元件。 每个可编程路由器元件具有连接多条输入线中的输入线的输入端和连接到多条输出行中的输出线的输出端。
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58.发明授权Scalable and parallel processing methods and structures for testing configurable interconnect network in FPGA device 失效用于测试FPGA器件中可配置互连网络的可扩展和并行处理方法和结构公开(公告)号：US06470485B1
公开(公告)日：2002-10-22
申请号：US09692694
申请日：2000-10-18
IPC分类号： H03K17693
CPC分类号： G01R31/318519
摘要： Configurable interconnect resources of field programmable gate arrays (FPGA's) are tested by configuring at least some of the lookup tables (LUT's), registers and input signal acquirers to implement one or more sequential state machines that feed back their current states via at least some of the interconnect conductors to the inputs of the LUT's. The fedback signals are decoded by the LUT's for defining next-states of the one or more sequential state machines. Each sequential state machine may be programmed to sequentially step through a number of unique states, where the unique states challenge capabilities of the interconnect conductors to toggle through combinations of different signal levels. The sequential state machines are exercised to sequentially step through plural ones of their unique states. At least one of the stepped-into states is sensed and analyzed after a predefined number of steps have been taken in order to determine whether the detected state matches the expected state for the predefined number of steps. If it does not, that is taken to indicate that a defect exists in the under-test FPGA. Plural sequential state machines can be exercised in parallel within a given FPGA so that large numbers of interconnect resources can be simultaneously challenged.
摘要翻译： 现场可编程门阵列（FPGA）的可配置互连资源通过配置至少一些查找表（LUT），寄存器和输入信号获取器来测试，以实现一个或多个顺序状态机，其通过至少一些 互连导体连接到LUT的输入端。 反馈信号由LUT解码，用于定义一个或多个顺序状态机的下一状态。 每个顺序状态机可以被编程为顺序地步进许多独特的状态，其中独特状态挑战互连导体的能力来切换不同信号电平的组合。 顺序状态机被执行以顺序地通过其独特状态中的多个状态。 在已经采取预定数量的步骤之后感测和分析至少一个步进状态，以便确定检测到的状态是否与预定数量的步骤的预期状态相匹配。 如果没有，则表示在测试中的FPGA中存在缺陷。 多个顺序状态机可以在给定的FPGA中并行运行，从而可以同时挑战大量互连资源。
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公开(公告)号：US06359466B1
公开(公告)日：2002-03-19
申请号：US08931798
申请日：1997-09-16
IPC分类号： H03K19173
CPC分类号： G06F7/5057 , G06F2207/3876
摘要： A circuit for providing a carry operation utilizing 3-input look up tables 502 and 504 and subsequent logic, the circuitry being configurable to provide an adder, a subtractor, an up/down counter, a pre-loadable counter, an accumulator, and a wide gate such as a large AND gate. To provide a carry out Ci+1, a multiplexer 506 has a first input receiving a carry in Ci, a select input coupled to the output of look up table 502, and a second input coupled to the output of look up table 504. The look up tables receive signals representing numbers Ai and Bi to be added or subtracted and ADD/SUB indicating if addition or subtraction is desired. The look up table 502 is programmed to provide Ai(+)Bi, while look up table 504 is programmed to provide Ai*Bi, (+) indicating a Boolean exclusive OR, and * a Boolean AND. With ADD selected, multiplexer 506 provides the carry out Ci+1 of the operation Ai+Bi+Ci. With SUB selected, a 2's complement of B is done before adding in the look up tables. The carry provided by multiplexer 506 is buffered by only one inverter. To provide a result of an addition or subtraction operation, Si, a multiplexer 508 has a first input receiving Ci, a second input receiving the inverse of Ci, and a select input receiving the output of look up table 502. An up/down counter, an accumulator and a preloadable counter can be formed by registering each Si output back to its corresponding Ai input. Additional components (510, 514, 516, 518) can be included to provide wide gating.
摘要翻译： 一种用于使用3输入查询表502和504以及后续逻辑提供进位操作的电路，该电路可配置为提供加法器，减法器，上/下计数器，预加载计数器，累加器和 宽门如大AND门。 为了提供进位Ci + 1，多路复用器506具有接收Ci中的进位的第一输入，耦合到查找表502的输出的选择输入和耦合到查找表504的输出的第二输入。 查找表接收表示要添加或减去的数字Ai和Bi的信号，并且指示是否需要加法或减法的ADD / SUB。 查找表502被编程以提供Ai（+）Bi，而查找表504被编程为提供指示布尔异或的Ai * Bi（+）和*布尔AND。 通过选择ADD，多路复用器506提供操作Ai + Bi + Ci的进位Ci + 1。 选择SUB后，在添加查询表之前完成B的2的补码。 由复用器506提供的进位由仅一个反相器缓冲。 为了提供加法或减法操作的结果，Si，多路复用器508具有接收Ci的第一输入接收Ci，接收Ci的倒数的第二输入和接收查询表502的输出的选择输入。上/下计数器 可以通过将每个Si输出回到其对应的Ai输入来形成累加器和可预加载计数器。 可以包括附加组件（510,514,516,518）以提供广泛的门控。
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60.发明授权Output buffer for making a high voltage (5.0 volt) compatible input/output in a low voltage (2.5 volt) semiconductor process 失效用于在低电压（2.5伏）半导体工艺中进行高电压（5.0伏）兼容输入/输出的输出缓冲器公开(公告)号：US06351157B1
公开(公告)日：2002-02-26
申请号：US09548171
申请日：2000-04-13
IPC分类号： H03K300
CPC分类号： H03K19/00315
摘要： An output buffer includes transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage (“the maximum tolerable voltage”), such as 2.7 volts, the transistors being configured to produce an output voltage significantly higher than the maximum tolerable voltage. The output buffer includes pull up transistors having source to drain paths connected in series to connect a voltage supply higher than the maximum tolerable voltage to the buffer output. The buffer further includes pull down transistors having source to drain paths connected in series to connect the buffer output to ground. The buffer further includes power supply circuitry to apply gate voltages to the pull up and pull down transistors so that the voltage potential from the source to drain of each of the pull up and pull down transistors is less than the maximum tolerable voltage. The power supply circuitry further controls gate voltages so that neither the gate to source, nor the gate to drain voltage for each of the pull up and pull down transistors exceeds the maximum tolerable voltage. Additionally, the power supply circuitry is itself configured so that voltage across leads of its transistor does not exceed the maximum tolerable voltage.
摘要翻译： 输出缓冲器包括允许最大栅极到源极，栅极到漏极或漏极到源极电压（“最大可容忍电压”）的晶体管，例如2.7伏，晶体管被配置为产生明显高于最大值的输出电压 耐受电压 输出缓冲器包括具有串联连接的源极至漏极路径的上拉晶体管，以将高于最大容许电压的电压源连接到缓冲器输出端。 该缓冲器还包括具有串联连接的源极至漏极路径的下拉晶体管，以将缓冲器输出端连接到地。 缓冲器还包括电源电路，以将栅极电压施加到上拉和下拉晶体管，使得每个上拉和下拉晶体管的源极到漏极的电压电位小于最大容许电压。 电源电路还控制栅极电压，使得每个上拉和下拉晶体管的栅极到源极以及栅极到漏极电压都不超过最大容许电压。 此外，电源电路本身被配置成使得其晶体管的引线两端的电压不超过最大容许电压。
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