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公开(公告)号：US20220283780A1
公开(公告)日：2022-09-08
申请号：US17461452
申请日：2021-08-30
发明人： Taro KANAO , Hayato GOTO , Ryo HIDAKA , Kosuke TATSUMURA
摘要： According to an embodiment, a calculation device includes a memory and one or more processors coupled to the memory and configured to alternately update, for elements each associated with first and second variables, the first and second variables, sequentially for unit times from an initial time to an end time. In an updating process for each unit time, the one or more processors are configured to: update, for each of the elements, the first variable based on the second variable; when the first variable is smaller than a first value, change the first variable to the first value and change the second variable to a third value; when the first variable is greater than a second value, change the first variable to the second value and change the second variable to the third value; and add an acceleration value calculated by a predetermined computation to the second variable.
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公开(公告)号：US20220276868A1
公开(公告)日：2022-09-01
申请号：US17633084
申请日：2021-06-08
发明人： Chao XU , Zhijun FAN , Ke XUE , Zuoxing YANG
摘要： This disclosure relates to a computing chip, a hashrate board, and a data processing apparatus. The computing chip includes a plurality of operation stages arranged in a pipeline configuration. Each operation stage includes: a first combinational logic circuit occupying a plurality of first cell points adjacent to each other, at least a portion of the first cell points being located in a first incomplete column; one or more second combinational logic circuits each occupying one or more second cell points, at least a portion of the second cell points being located in a second incomplete column; and a plurality of registers each occupying a plurality of third cell points, at least a portion of the third cell points being located in the first incomplete column or the second incomplete column. The first cell points, the second cell points, and third cell points occupy equal areas on the computing chip.
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公开(公告)号：US20220263525A1
公开(公告)日：2022-08-18
申请号：US17733338
申请日：2022-04-29
摘要： A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.
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公开(公告)号：US20220188077A1
公开(公告)日：2022-06-16
申请号：US17526010
申请日：2021-11-15
申请人： FUJITSU LIMITED
发明人： MAKIKO ITO
摘要： An arithmetic processing device includes one or more memories; and one or more processors includes execute an operation of fixed-point number data, acquire statistical information that indicates a distribution of positions of most significant bits of a plurality of fixed-point number data obtained by the operation, update, based on the statistical information, a range for restriction of bit width of the plurality of fixed-point number data to be used for the operation, estimate respective data amount after compression of the plurality of fixed-point number data by a plurality of compression methods based on the statistical information, determine a compression method by which data amount after compression of the plurality of fixed-point number data is minimum among plurality of compression methods, transfer the plurality of fixed-point number data compressed by the compression method to the one or more memories.
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公开(公告)号：US11342944B2
公开(公告)日：2022-05-24
申请号：US17029652
申请日：2020-09-23
摘要： A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.
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公开(公告)号：US20220121448A1
公开(公告)日：2022-04-21
申请号：US17074739
申请日：2020-10-20
发明人： Christ Baronne , Dean E. Walker
摘要： Devices and techniques for short-thread rescheduling in a processor are described herein. When an instruction for a thread completes, a result is produced. The condition that the same thread is scheduled in a next execution slot and that the next instruction of the thread will use the result can be detected. In response to this condition, the result can be provided directly to an execution unit for the next instruction.
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47.发明申请公开(公告)号：US20220108211A1
公开(公告)日：2022-04-07
申请号：US17095976
申请日：2020-11-12
IPC分类号： G06N20/00 , G06F7/57 , G06F30/367
摘要： A method and system for integrating Field Programmable Analog Array (FPAA) with Artificial Intelligence (AI) is disclosed. In some embodiments, the method includes automatically creating, by an AI model, a function by auto connecting a first set of computation elements from a plurality of computational elements in an FPAA, in response to receiving an input. The method further includes receiving a feedback comprising a first accuracy level associated with the output. The method further includes automatically adjusting at least one of a plurality of control parameters to modify the function to generate an adjusted output corresponding to the input, based on the first accuracy level associated with the output.
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公开(公告)号：US20220100565A1
公开(公告)日：2022-03-31
申请号：US17206660
申请日：2021-03-19
申请人： HITACHI, LTD.
发明人： Kohei TATARA , Yoshinori OHIRA , Masakuni AGETSUMA
摘要： The computer system includes a node including a processor and a memory, and the processor and the memory serve as arithmetic operation resources. The computer system has an application program that operates using the arithmetic operation resources, and a storage controlling program that operates using the arithmetic operation resources for processing data to be inputted to and outputted from a storage device by the application program. The computer system has use resource amount information that associates operation states of the application program and the arithmetic operation resources that are to be used by the application program and the storage controlling program. The computer system changes allocation of the arithmetic operation resources to the application program and the storage controlling program used by the application program on the basis of an operation state of the application program and the use resource amount information.
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公开(公告)号：US20220092736A1
公开(公告)日：2022-03-24
申请号：US17543075
申请日：2021-12-06
申请人： Nvidia Corporation
发明人： Shiqiu Liu , Matthieu Le , Andrew Tao
摘要： Apparatuses, systems, and techniques to enhance video are disclosed. In at least one embodiment, one or more neural networks are used to create a higher resolution video using upsampled frames from a lower resolution video.
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公开(公告)号：US20220004155A1
公开(公告)日：2022-01-06
申请号：US17284781
申请日：2019-10-24
申请人： OMRON Corporation
发明人： Ko KAWAI , Takahiro TOKU
摘要： This control system includes: a first arithmetic unit for doing cyclic execution of a first task to which one or a plurality of processes are allocated using a first control cycle; and a second arithmetic unit for doing cyclic execution of a second task to which one or a plurality of processes are allocated using a second control cycle that is longer than the first control cycle. For the first task, a first data collection process with a first input data as the target and a corresponding first data processing process are allocated. Depending on the setting via the support device, a second data collection process with a second input data as the target and a corresponding second data processing process are allocated to either of the first task and the second task.
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