-
公开(公告)号：US20200075638A1
公开(公告)日：2020-03-05
申请号：US16336738
申请日：2018-09-12
Inventor： Mang ZHAO
Abstract: A pull-down circuit of a gate driving unit includes: a first thin film transistor having a first gate to which a scan direction signal is inputted, a first source and a first drain to which a clock signal is inputted; a second thin film transistor having a second gate coupled to the first source, a second source coupled to a pull-down control node and a second drain to which a first direct-current voltage is inputted; a third thin film transistor having a third gate to which a first control signal is inputted, a third source coupled to the pull-down control node and a third drain coupled to a second direct-current voltage; and a fourth thin film transistor having a fourth gate coupled to the pull-down control node, a fourth source coupled to an output node and a fourth drain coupled to the second direct-current voltage.
-
公开(公告)号：US20200020290A1
公开(公告)日：2020-01-16
申请号：US15667670
申请日：2017-04-18
Inventor： Mang ZHAO
IPC: G09G3/36 , G02F1/1345
Abstract: The present disclosure provides a scan-driving circuit and a liquid crystal display, which comprises a scan-level-signal-output module, a present-stage cascaded-signal-output module, and a present-stage scanning-signal-output module. The scan-level-signal-output module is used for generating a scanning level signal and for performing a latching operation on the scanning level signal. A forward/reverse scanning control signal is used for controlling the scanning drive unit be on a forward-driving mode or a reverse-driving mode.
-
公开(公告)号：US20180336856A1
公开(公告)日：2018-11-22
申请号：US15548414
申请日：2017-04-18
IPC: G09G3/36 , G02F1/133 , H03K19/094
CPC classification number: G09G3/3674 , G02F1/13306 , G09G2310/0264 , G09G2310/0286 , G09G2310/0294 , G11C19/28 , H03K19/09425
Abstract: A scanning driving circuit includes a scanning-level-signal-generation module and a scanning-signal-output-module. The scanning-level-signal-generation module is configured to input an (N−1)th stage scanning signal, an (N+1)th stage scanning signal, and a reset signal, generate a scanning level signal based on the (N−1)th stage scanning signal, the (N+1)th stage scanning signal, and the reset signal, and hold the scanning level signal. The scanning-signal-output-module, connected to the scanning-level-signal-generation module, is configured to input a clock signal, and configured to output a scanning signal based in the scanning level signal and the clock signal.
-
公开(公告)号：US20180240432A1
公开(公告)日：2018-08-23
申请号：US15790006
申请日：2017-10-22
Inventor： Mang ZHAO
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2310/0205 , G09G2310/0283 , G09G2310/0286 , G09G2310/0291 , G09G2310/062 , G09G2310/08
Abstract: A gate driver on array (GOA) circuit includes a plurality of stages of GOA units cascaded. A first control latch module, a signal processing module, and a second control latch module of an Nth stage GOA unit generate an Nth stage dipulse gate driving signal and an Nth stage cascade signal according to clock signals, and an (N−2)th or (N+2)th stage cascade signal. For the clock signals corresponding to adjacent two stages of the GOA units, a first clock signal is delayed for a predetermined period of time with respect to a second clock signal. The two dipulse gate driving signals generated by the adjacent two stages of the GOA units partially overlap.
-
公开(公告)号：US20180190181A1
公开(公告)日：2018-07-05
申请号：US15316158
申请日：2016-11-16
Inventor： Mang ZHAO
IPC: G09G3/20
CPC classification number: G09G3/2096 , G09G3/20 , G09G2310/0283 , G09G2310/067
Abstract: The present disclosure relates to a scanning driving circuit including a plurality of cascaded-connected scanning driving units. Each of the scanning driving unit includes a forward-backward scanning circuit, a first and a second input circuit outputting first and second input signals; a pull-down circuit outputting first or second pull-down signals and pulling down or charging a first pull-down control signal point or a second pull-down control signal point; a first and a second control circuit charging or pulling down the first pull-down control signal point or the second pull-down control signal point; and the first and the second output circuit generating the first and the second scanning driving signals for the first and the second scanning line to drive pixel cells.
-
Patent Agency Ranking
公开(公告)号：US20180061348A1
公开(公告)日：2018-03-01
申请号：US14917947
申请日：2016-02-22
Inventor： Mang ZHAO
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/3614 , G09G2300/0408 , G09G2310/0218 , G09G2310/061 , G09G2310/08 , G11C19/28
Abstract: The present disclosure relates to a gate driving circuit and the LCD thereof. The input circuit generates second control signals in accordance with up-level normal-phase scanning driving signals, up-level inverting-phase scanning driving signals, and first control signals outputted by the latch circuit. The reset and control circuit generates third control signals in accordance with reset signals, the first control signals, and the second control signals. The inverting circuit performs an inverting process at least once toward the third control signals, and generates fourth control signals, the output circuit generates current-level normal-phase scanning driving signals and the current-level inverting-phase scanning driving signals in accordance with the fourth control signals and first clock signals, The latch circuit generates the first control signals in accordance with the third control signals and second clock signals, and latches or changes a voltage state of the third control signals in accordance with the second clock signals.
-
公开(公告)号：US20180053482A1
公开(公告)日：2018-02-22
申请号：US15802924
申请日：2017-11-03
Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Juncheng XIAO , Mang ZHAO
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2330/04
Abstract: A GOA circuit and a liquid crystal device (LCD) are disclosed. The GOA circuit includes a plurality of GOA units and a control module. Each of the cascaded GOA units is configured for charging corresponding horizontal scanning lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second control clock. After the horizontal scanning lines are fully charged by the GOA circuit, the control module is configured for resetting the gate driving signals to be at the first level, i.e., the invalid level, via the turn-on pulse signals and the negative-voltage constant-voltage source.
-
公开(公告)号：US20180046048A1
公开(公告)日：2018-02-15
申请号：US14916261
申请日：2016-02-24
Inventor： Mang ZHAO
IPC: G02F1/1362 , H01L27/12 , G11C19/28 , G09G3/36
CPC classification number: G09G3/3674 , G02F1/136286 , G09G3/3648 , G09G3/3677 , G09G3/3696 , G09G2300/0408 , G09G2310/0283 , G09G2310/0286 , G11C19/28 , H01L27/124 , H01L27/1255
Abstract: A GOA circuit includes GOA circuit units. A holding module is substituted for a capacitor in each GOA circuit unit. A second transistor in the holding module is turned on when a scanning signal does not produce a pulse so that voltage imposed in a first control node is held by a first transistor and a third transistor. Because the transistors form a passage between the first control node and a first constant voltage, the voltage imposed on the first control node does not vary due to electricity leakage. Because a second capacitor is coupled with the first control node, the pulse of the scanning signal output by the GOA circuit unit reaches to an ideal high voltage level. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.
-
公开(公告)号：US20170162149A1
公开(公告)日：2017-06-08
申请号：US14785043
申请日：2015-08-10
Inventor： Mang ZHAO , Juncheng XIAO , Yong TIAN
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3266 , G09G3/3696 , G09G2300/043 , G09G2310/0267 , G09G2310/0286
Abstract: The present invention provides a scanning driving circuit for executing a driving operation to cascaded scanning lines, the scanning driving circuit includes a pull-down control module, a pull-down module, a reset module, a down link module, a first bootstrap capacitor, a constant low voltage level source, and a constant high voltage level source; wherein a cascading manner of the clock signal is determined according to a scanning order of the scanning driving circuit, for the reset module to pull up the corresponding scanning signal of the scanning line. The structure of the scanning driving circuit of the present invention is simple and highly dependable.
-
公开(公告)号：US20170153522A1
公开(公告)日：2017-06-01
申请号：US14773355
申请日：2015-08-11
IPC: G02F1/1362 , H01L29/786 , G01R31/28 , G02F1/1368 , G09G3/00 , G02F1/1345 , H01L27/12 , H01L21/66
CPC classification number: G02F1/136286 , G01R31/2825 , G02F1/13454 , G02F1/1368 , G02F2001/136254 , G02F2202/104 , G09G3/006 , G09G2330/12 , H01L22/34 , H01L27/1222 , H01L27/124 , H01L29/78672
Abstract: A baseplate circuit is disclosed. The baseplate comprises an IC region, a plurality of WOA regions, a plurality of GOA regions, and a plurality of switches. Each WOA region comprises a plurality of baseplate conducting wires, each of the baseplate conducting wires is electrically connected with the IC region. Each GOA region comprises a plurality of gate lines, each of the gate lines is electrically connected with one of the baseplate conducting wires. Each of the switches is used to electrically connect one of the gate lines and one of the baseplate conducting wires.
-
-
-
-
-
-
-
-
-
Search Results
52
records
(took 0.039 seconds)
