公开(公告)号：US20210202254A1

公开(公告)日：2021-07-01

申请号：US17200133

申请日：2021-03-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Yun PENG ,  Chung-Chi KO ,  Keng-Chu LIN

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/02

Abstract: A device includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first conductor is in the first dielectric layer. The etch stop layer is over the first dielectric layer. The etch stop layer has a first surface facing the first dielectric layer and a second surface facing away from the first dielectric layer, and a concentration of carbon in the etch stop layer periodically varies from the first surface to the second surface. The second dielectric layer is over the etch stop layer. The second conductor is in the second dielectric layer and the etch stop layer and electrically connected to the first conductor.

公开(公告)号：US20210193506A1

公开(公告)日：2021-06-24

申请号：US16937237

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin LIANG ,  Chen-Han WANG ,  Keng-Chu LIN ,  Tetsuji UENO ,  Ting-Ting CHEN

IPC: H01L21/768 ,  H01L29/66

Abstract: The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.

公开(公告)号：US20190165127A1

公开(公告)日：2019-05-30

申请号：US15883684

申请日：2018-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Lun CHENG ,  Chih-Hao WANG ,  Keng-Chu LIN ,  Shi-Ning JU

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device is disclosed that includes a plurality of isolation regions. A fin is arranged between the plurality of isolation regions. One of the plurality of isolation regions includes a first atomic layer deposition (ALD) layer, a second ALD layer, a flowable chemical vapor deposition (FCVD) layer, and a third ALD layer. The first ALD layer includes a first trench. The second ALD layer is formed in the first trench of the first ALD layer. The FCVD layer is formed in the first trench of the first ALD layer and on the second ALD layer. The third ALD layer is formed on the FCVD layer.

公开(公告)号：US20190103276A1

公开(公告)日：2019-04-04

申请号：US16015743

申请日：2018-06-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Yun PENG ,  Chung-Chi KO ,  Keng-Chu LIN

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/762

Abstract: A method includes forming an interlayer dielectric (ILD) and a gate structure over a substrate. The gate structure is surrounded by the ILD. The gate structure is etched to form a recess. A first dielectric layer is deposited over sidewalls and a bottom of the recess and over a top surface of the ILD using a first Si-containing precursor. A second dielectric layer is deposited over and in contact with the first dielectric layer using a second Si-containing precursor different from the first Si-containing precursor. A third dielectric layer is deposited over and in contact with the second dielectric layer using the first Si-containing precursor. Portions of the first, second, and third dielectric layer over the top surface of the ILD are removed.