公开(公告)号：US20180246678A1

公开(公告)日：2018-08-30

申请号：US15969042

申请日：2018-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn Cha ,  HOl-JU CHUNG ,  UK-SONG KANG

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0679 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/106 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/52

Abstract: A method of scrubbing errors from a semiconductor memory device including a memory cell array and an error correction circuit, can be provided by accessing a page of the memory cell array to provide a data that includes sub units that are separately writable to the page of memory and to provide parity data configured to detect and correct a bit error in the data and selectively enabling write-back of a selected sub unit of the data responsive to determining that the selected sub unit of data includes a correctable error upon access as part of an error scrubbing operation.

公开(公告)号：US20180159558A1

公开(公告)日：2018-06-07

申请号：US15789653

申请日：2017-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Uhn Cha ,  Ye-Sin Ryu ,  Young-Sik Kim ,  Su-Yeon Doo

IPC: H03M13/29 ,  H03M13/09

CPC classification number: H03M13/2906 ,  H03M13/09

Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.

公开(公告)号：US09990163B2

公开(公告)日：2018-06-05

申请号：US15290339

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Uk-Song Kang

IPC: G11C11/34 ,  G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G11C11/16

CPC classification number: G06F3/0679 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/106 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/52

Abstract: A method of scrubbing errors from a semiconductor memory device including a memory cell array and an error correction circuit, can be provided by accessing a page of the memory cell array to provide a data that includes sub units that are separately writable to the page of memory and to provide parity data configured to detect and correct a bit error in the data and selectively enabling write-back of a selected sub unit of the data responsive to determining that the selected sub unit of data includes a correctable error upon access as part of an error scrubbing operation.