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    Chassis interconnect for an electronic device
    41.
    发明授权
    Chassis interconnect for an electronic device 有权

    公开(公告)号：US11445608B2

    公开(公告)日：2022-09-13

    申请号：US16903845

    申请日：2020-06-17

    Applicant: Intel Corporation

    Inventor： Chee How Lim ,  Eng Huat Goh ,  Jon Sern Lim ,  Khai Ern See ,  Min Suet Lim ,  Tin Poay Chuah ,  Yew San Lim

    IPC: H05K1/14 ,  H01R12/61 ,  H05K1/11

    Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.

    Board to board interconnect
    42.
    发明授权
    Board to board interconnect 有权

    公开(公告)号：US11304299B2

    公开(公告)日：2022-04-12

    申请号：US17008222

    申请日：2020-08-31

    Applicant: Intel Corporation

    Inventor： Chee Ling Wong ,  Wil Choon Song ,  Khang Choong Yong ,  Eng Huat Goh ,  Mohd Muhaiyiddin Bin Abdullah ,  Tin Poay Chuah

    IPC: H05K1/11 ,  H05K1/14 ,  H05K1/02

    Abstract: A system for board-to-board interconnect is described herein. The system includes a first printed circuit board (PCB) having a first recess along a first edge of the first PCB that exposes a first solder pad on a layer of the first PCB. The system also includes a second PCB having a second recess along a second edge of the second PCB that exposes a second solder pad on a layer of the second PCB. The second recess is complementary to the first recess to allow the first PCB to mate with the second PCB. The first solder pad is aligned with the second solder pad when the first PCB is mated with the second PCB. The system additionally includes an assembly configured to electronically couple the first solder pad with the second solder pad.

    CHASSIS INTERCONNECT FOR AN ELECTRONIC DEVICE
    45.
    发明申请
    CHASSIS INTERCONNECT FOR AN ELECTRONIC DEVICE 有权

    公开(公告)号：US20210100101A1

    公开(公告)日：2021-04-01

    申请号：US16903845

    申请日：2020-06-17

    Applicant: Intel Corporation

    Inventor： Chee How Lim ,  Eng Huat Goh ,  Jon Sern Lim ,  Khai Ern See ,  Min Suet Lim ,  Tin Poay Chuah ,  Yew San Lim

    IPC: H05K1/14 ,  H05K1/11 ,  H01R12/61

    Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.

    COMBINATION STIFFENER AND CAPACITOR
    47.
    发明申请
    COMBINATION STIFFENER AND CAPACITOR 有权

    公开(公告)号：US20210035738A1

    公开(公告)日：2021-02-04

    申请号：US16306889

    申请日：2016-07-02

    Applicant: Intel Corporation

    Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

    IPC: H01G4/224 ,  H05K1/02 ,  H01G4/005 ,  H01L23/16 ,  H05K3/28 ,  H01L49/02

    Abstract: Electronic device package stiffener and capacitor technology is disclosed. A combination stiffener and capacitor can include a structural material configured to be coupled to a substrate. The structural material can have a shape configured to provide mechanical support for the substrate. The combination stiffener and capacitor can also include first and second electrodes forming a capacitor. An electronic device package and a package substrate configured to receive the combination stiffener and capacitor are also disclosed.

    Package jumper interconnect
    49.
    发明授权
    Package jumper interconnect 有权

    公开(公告)号：US10785872B2

    公开(公告)日：2020-09-22

    申请号：US16263370

    申请日：2019-01-31

    Applicant: Intel Corporation

    Inventor： Eng Huat Goh ,  Hoay Tien Teoh

    IPC: H05K1/11 ,  H05K1/02 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

    Abstract: A jumper may be adapted to transmit an electrical signal. The jumper may be included in a system on a chip. The system on a chip may include a substrate, and the substrate may include one or more routing layers. The jumper may be included in the one or more routing layers of the substrate. A first interconnect may be positioned on a first side of the system on a chip, and a second interconnect may be positioned on a second side of the system on a chip. The jumper may be in electrical communication with the first interconnect, and may be in electrical communication with the second interconnect. The jumper may be electrically isolated from other components of the system on a chip, such as one or more die coupled to the substrate.

    FIBER WEAVE-SANDWICHED DIFFERENTIAL PAIR ROUTING TECHNIQUE
    50.
    发明申请
    FIBER WEAVE-SANDWICHED DIFFERENTIAL PAIR ROUTING TECHNIQUE 审中-公开

    公开(公告)号：US20200137886A1

    公开(公告)日：2020-04-30

    申请号：US16565639

    申请日：2019-09-10

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

    IPC: H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H05K3/40

    Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.

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