公开(公告)号：US5430390A

公开(公告)日：1995-07-04

申请号：US245309

申请日：1994-05-17

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

公开(公告)号：US5397939A

公开(公告)日：1995-03-14

申请号：US094677

申请日：1993-07-20

Applicant: Kathryn E. Gordon ,  Andrew K. Chan

Inventor： Kathryn E. Gordon ,  Andrew K. Chan

IPC: G11C17/18 ,  H01L21/768 ,  H01L23/525 ,  H03K19/173 ,  G06F7/38

CPC classification number: H01L21/76888 ,  G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: The invention allows programming an antifuse so as to reduce the antifuse resistance and the standard deviation of the resistance without increasing the programming current. This is achieved by passing current pulses of the opposite polarity through the antifuse. In some embodiments, the magnitude of the second pulse is lower than the magnitude of the first pulse. Further, if the antifuse is formed on a semiconductor substrate with one electrode on top of the other electrode and on top of the substrate, the current during the first pulse flows from the top electrode to the bottom electrode and not vice versa. A programming circuitry is provided that allows to program antifuses in a programmable circuit. A driver circuit is connected to each "horizontal" channel and each "vertical" channel. Each driver circuit is controlled by data in the driver circuit. The driver circuits are connected into shift registers so that all the data can be entered from one, two, three or four inputs. No decoding circuitry is necessary. Before programming, the drivers precharge all the channels to an intermediate voltage. During programming, the channels that are not directly connected to the antifuse being programmed are switched to high impedance. As a result, the power consumption is reduced and the programming proceeds faster.

Abstract translation: 本发明允许对反熔丝进行编程，以便在不增加编程电流的情况下降低反熔丝电阻和电阻的标准偏差。 这是通过使相反极性的电流脉冲通过反熔丝来实现的。 在一些实施例中，第二脉冲的幅度低于第一脉冲的幅度。 此外，如果反熔丝形成在半导体衬底上，一个电极在另一个电极的顶部和衬底上，则第一脉冲期间的电流从顶部电极流向底部电极，反之亦然。 提供了一种编程电路，其允许在可编程电路中编程反熔丝。 驱动电路连接到每个“水平”通道和每个“垂直”通道。 每个驱动电路由驱动电路中的数据控制。 驱动器电路连接到移位寄存器，以便所有的数据可以从一个，两个，三个或四个输入输入。 不需要解码电路。 在编程之前，驱动器将所有通道预充电至中间电压。 在编程期间，未直接连接到正在编程的反熔丝的通道切换到高阻抗。 因此，功耗降低，编程进行得更快。

公开(公告)号：US5079450A

公开(公告)日：1992-01-07

申请号：US582013

申请日：1990-09-13

Applicant: Vincent K. Z. Win ,  Andrew K. Chan

Inventor： Vincent K. Z. Win ,  Andrew K. Chan

IPC: H03K3/037 ,  H03K3/356 ,  H03K19/177

CPC classification number: H03K3/356017 ,  H03K19/17716 ,  H03K3/037

Abstract: A self-latching logic gate is disclosed which includes a first logic gate circuit for generating an output signal representative of a function of two or more input signals. The first logic gate circuit includes a first logic gate having at least two transistors, each transistor having first, second and third terminals. The first terminals of each transistor are connected to provide an output terminal for the self-latching logic gate and the first logic gate circuit. The second terminals of the transistors provide first and second data input terminals for the logic gate circuit. The third terminals of each transistor are connected to a common termination (i.e. ground). First and second complementary mode transistors are provided. Each includes first, second and third terminals, with the first terminal of the first transistor being connected to a source of electrical potential, the second terminals of the first and the second transistors being connected to each other to provide a common input terminal for the first and second transistors, the third terminal of the first transistor and the first terminal of the second transistor being connected to the output terminal of the first logic gate, and the third terminal of the second transistor being connected to ground. A second logic gate circuit is provided for including a second logic gate having first and second input terminals, the first input terminal being connected to the output terminal of the first logic gate circuit, the second input terminal providing a latch input terminal for the self-latching gate, and the output terminal of the second logic gate being connected to the common input terminal of the first and second transistors. In a specific embodiment, the present invention provides a NOR gate with a self-latching output, with minimal parts count and power consumption, which is suitable for use in a PAL system. In further more specific embodiments, the invention includes circuitry for verifying the state of the PAL array, circuitry for changing the polarity of the array output and circuitry for providing system security all with minimal parts counts and power consumption.

公开(公告)号：US4914322A

公开(公告)日：1990-04-03

申请号：US285721

申请日：1988-12-16

Applicant: Vincent K. Z. Win ,  Andrew K. Chan

Inventor： Vincent K. Z. Win ,  Andrew K. Chan

IPC: H03K19/177

CPC classification number: H03K19/17716

Abstract: Polarity option control logic is disclosed which provides an optimized design for a macrocell of a programmable logic array with a minimal parts count.The invention is designed for use with a register of the macrocell having first and second input paths, the first input path including an inverter, and first and second switches in each path respectively. The polarity option control logic of the present invention includes a first logic circuit for receiving a clock input and a polarity input signal and controlling the activation of the first switch in response thereto and a second logic circuit for receiving the clock input and an inverted polarity input signal and controlling the activation of the second switch in response thereto. When the polarity input signal is in a first state, the first input path is enabled via the first switch in accordance with the clock signal and when the polarity input signal is in a second state, the second input path is enabled via the second switch in accordance with the clock signal.In a particular embodiment, a macrocell is provided including polarity option control logic, a bypass option, a high speed multiplexer and an advantageous preload circuit that minimizes parasitic capacitances at the register input. Thus, a macrocell constructed in accordance with the present teachings, can be configured in a register mode with set, reset and preload features or a logic mode with an optimized speed path for both modes of operation.

Abstract translation: 公开了极性选项控制逻辑，其为具有最小部件数量的可编程逻辑阵列的宏单元提供优化设计。 本发明设计用于具有第一和第二输入路径的宏小区的寄存器，第一输入路径包括逆变器，以及每个路径中的第一和第二开关。 本发明的极性选择控制逻辑包括：第一逻辑电路，用于接收时钟输入和极性输入信号，并响应于此控制第一开关的启动;以及第二逻辑电路，用于接收时钟输入和反相极性输入 信号并且响应于此控制第二开关的激活。 当极性输入信号处于第一状态时，根据时钟信号经由第一开关使第一输入路径被使能，并且当极性输入信号处于第二状态时，第二输入路径经由第二开关被使能 按照时钟信号。 在特定实施例中，提供宏单元，其包括极性选项控制逻辑，旁路选项，高速多路复用器和使寄存器输入端的寄生电容最小化的有利的预加载电路。 因此，根据本教导构造的宏单元可以被配置为具有设定，复位和预加载功能的寄存器模式或具有用于两种操作模式的优化速度路径的逻辑模式。

公开(公告)号：US4789951A

公开(公告)日：1988-12-06

申请号：US864185

申请日：1986-05-16

Applicant: John M. Birkner ,  Danesh M. Tavana ,  Andrew K. Chan ,  Sing Y. Wong

Inventor： John M. Birkner ,  Danesh M. Tavana ,  Andrew K. Chan ,  Sing Y. Wong

IPC: H03K19/177 ,  H03K3/037 ,  G06F7/38 ,  H03K19/173

CPC classification number: H03K3/037

Abstract: A programmable array logic cell 60 including a sum-of-products array having a single OR gate 70 for providing a sum signal, and including an XOR gate 80 for combining the sum signal with a product signal provided by an AND gate 78 from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.

Abstract translation: 一种可编程阵列逻辑单元60，其包括具有用于提供和信号的单或门70的产品和阵列阵列，并且包括用于将和信号与由和门78从选定阵列提供的乘积信号组合的XOR门80 输入和/或反馈信号。 产品信号可以是用于JK触发器配置的先前状态输出信号Q，或用于可编程输出信号极性的其他配置的强制高或低信号。

公开(公告)号：US4670708A

公开(公告)日：1987-06-02

申请号：US635861

申请日：1984-07-30

Applicant: Bob Bosnyak ,  Albert Chan ,  Mark Fitzpatrick ,  Gary Gouldsberry ,  Cyrus Tsui ,  Andrew K. Chan

Inventor： Bob Bosnyak ,  Albert Chan ,  Mark Fitzpatrick ,  Gary Gouldsberry ,  Cyrus Tsui ,  Andrew K. Chan

IPC: G11C29/00 ,  G01R31/02 ,  G11C17/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/50

CPC classification number: G11C29/50008 ,  G01R31/025 ,  G11C29/02 ,  G11C29/50 ,  G11C17/14

Abstract: Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a pair of reference fusible links to detect the presence or absence of a short circuit.

Abstract translation: 提供电路用于测试易熔链路周围短路的易熔链路阵列。 每个链路都是电隔离的，并与一对基准可熔链路进行比较，以检测短路的存在与否。