公开(公告)号：US07433231B2

公开(公告)日：2008-10-07

申请号：US11411376

申请日：2006-04-26

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer.

摘要翻译： 描述与非易失性存储器单元相关联的多个选择门。 各种实施例包括多个选择栅极结构，工艺和操作及其对存储器件，模块和系统的适用性。 在一个实施例中描述了存储器阵列。 存储器阵列包括多个与多个非易失性存储器单元串联耦合的选择栅极。 第一选择栅极包括电连接在一起的控制栅极和浮置栅极，第二选择栅极包括由电介质层电隔离的控制栅极和浮置栅极。

公开(公告)号：US07411832B2

公开(公告)日：2008-08-12

申请号：US11436323

申请日：2006-05-18

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C16/3459 ,  G11C8/10 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial programming pulse, a verify operation determines if the cell has been programmed. If the cell is still erased, the initial programming voltage is increased by the step voltage. The step voltage for the lowest word line near the source line is lower than the step voltage for the word line closest to the drain line.

摘要翻译： 一种非易失性存储器件，其改变阵列的源极侧和阵列的漏极侧之间的编程阶跃电压。 在初始编程脉冲之后，验证操作确定单元是否已被编程。 如果单元仍然被擦除，则初始编程电压通过阶跃电压增加。 源极线附近的最低字线的阶跃电压低于最靠近漏极线的字线的阶跃电压。

公开(公告)号：US20080170424A1

公开(公告)日：2008-07-17

申请号：US12052882

申请日：2008-03-21

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C5/06

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

摘要翻译： 提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。 第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部 并且将第二块布置在其另一部分上。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存​​储单元单元的结构不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

公开(公告)号：US20080158952A1

公开(公告)日：2008-07-03

申请号：US11646815

申请日：2006-12-28

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell to a first Vt within a lowermost Vt range. The method includes programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell. The method includes programming the upper page of the first wordline cell such that the first Vt is increased to a second Vt, wherein the second Vt is within a Vt range which is then a lowermost Vt range and is positive.

摘要翻译： 本公开的实施例提供用于将非易失性多电平存储器单元的阵列编程为多个阈值电压范围的方法，装置，模块和系统。 一种方法包括编程第一字线单元的下页以将第一字线单元的阈值电压（Vt）增加到最低Vt范围内的第一Vt。 该方法包括在编程第一字线单元的上部页之前对第二字线单元的下部页进行编程。 所述方法包括对所述第一字线单元的上部页进行编程，使得所述第一Vt增加到第二Vt，其中所述第二Vt在Vt范围内，其为最低Vt范围并且为正。

公开(公告)号：US07372742B2

公开(公告)日：2008-05-13

申请号：US11726832

申请日：2007-03-23

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/344 ,  G11C16/0483 ,  G11C16/3445

摘要： The erase and verify method performs an erase operation and an erase verify read operation. If the erase verify read operation fails because unerased memory cells have been found, a normal memory read operation is performed in order to determine which memory cells are still programmed. A selective erase operation is then performed on the memory cells such that only the rows that comprise unerased memory cells undergo additional erase operations.

公开(公告)号：US20080056008A1

公开(公告)日：2008-03-06

申请号：US11513891

申请日：2006-08-31

申请人： Seiichi Aritome ,  Alessandro Torsi ,  Carlo Musilli

发明人： Seiichi Aritome ,  Alessandro Torsi ,  Carlo Musilli

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a predetermined distance of the drain side of the memory block array. If the selected word line is closer to the source side, a lower read pass voltage is used. In another embodiment, the cells on the word lines closer to the drain side of the memory block array are erased to a lower threshold voltage than the memory cells on the remaining word lines.

摘要翻译： 在读取操作期间通过增加通过串行存储单元的漏极电流来减少读取失败。 在一个实施例中，当所选字线在存储器块阵列的漏极侧的预定距离内时，对未选择的字线使用更高的读通过电压来实现。 如果所选字线更靠近源极侧，则使用较低的读通过电压。 在另一个实施例中，更靠近存储器块阵列的漏极侧的字线上的单元被擦除到比剩余字线上的存储器单元更低的阈值电压。

公开(公告)号：US07332762B2

公开(公告)日：2008-02-19

申请号：US11617425

申请日：2006-12-28

申请人： Hiroshi Watanabe ,  Hiroshi Nakamura ,  Kazuhiro Shimizu ,  Seiichi Aritome ,  Toshitake Yaegashi ,  Yuji Takeuchi ,  Kenichi Imamiya ,  Ken Takeuchi ,  Hideko Oodaira

发明人： Hiroshi Watanabe ,  Hiroshi Nakamura ,  Kazuhiro Shimizu ,  Seiichi Aritome ,  Toshitake Yaegashi ,  Yuji Takeuchi ,  Kenichi Imamiya ,  Ken Takeuchi ,  Hideko Oodaira

IPC分类号： H01L27/108 ,  H01L29/73

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

公开(公告)号：US20070291542A1

公开(公告)日：2007-12-20

申请号：US11452698

申请日：2006-06-14

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/3409 ,  G11C16/3454

摘要： A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells utilizing a drain-side self boost, modified drain-side self boost or local self boost process that increases the pass voltage (Vpass_high) on a word line on the source line side of a memory cells selected for programming to boost the voltage on the source of the adjacent blocking cell of the string. This drives the adjacent blocking cell further into cutoff and increases boosting by decreasing channel leakage to the source line during programming.

摘要翻译： 描述了NAND​​架构非易失性存储器件和编程过程，其利用漏极侧自升压，修改的漏极侧自升压或局部自升压工艺来编程非易失性存储器单元串的各个单元，其增加通过电压 （Vpass_high）在选择用于编程的存储器单元的源极侧的字线上升高串的相邻阻塞单元的源极上的电压。 这样在编程期间通过减少通道泄漏到源极线来驱动相邻的阻塞单元进一步截止并增加升压。

公开(公告)号：US20070279989A1

公开(公告)日：2007-12-06

申请号：US11448063

申请日：2006-06-06

申请人： Seiichi Aritome

发明人： Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427

摘要： A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data. The method: programs the lower page of predetermined memory cells with first predetermined data and the upper page with second predetermined data. One of the lower page or the upper page of the predetermined memory cells is reprogrammed with the first or second predetermined data, respectively.

摘要翻译： 一种用于编程包括多个存储单元的非易失性存储器阵列的方法。 每个单元适用于存储数据的下页和上页。 该方法：利用第一预定数据对预定存储单元的下页进行编程，并且利用第二预定数据对上页进行编程。 分别使用第一或第二预定数据重新编程预定存储单元的下页或上页中的一个。

公开(公告)号：US20070247908A1

公开(公告)日：2007-10-25

申请号：US11407227

申请日：2006-04-19

申请人： Seiichi Aritome ,  Akira Goda

发明人： Seiichi Aritome ,  Akira Goda

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated with a selected block of an array of memory cells and a second, different, potential is supplied to other source lines not associated with that block. By supplying a different potential to source lines of unselected blocks, current leakage can be mitigated.

摘要翻译： 利用NAND架构的非易失性存储器件适于执行读取操作，其中将第一电位提供给与存储器单元阵列的所选块相关联的源极线，并且将第二不同的电位提供给不相关的其它源极线 与那个块。 通过向未选择的块的源极线提供不同的电位，可以减轻电流泄漏。