公开(公告)号：US20170134021A1

公开(公告)日：2017-05-11

申请号：US15039570

申请日：2014-11-07

Applicant: SANECHIPS TECHNOLOGY CO., LTD

Inventor： Qingwei Shi

IPC: H03K17/94 ,  H03K17/945

CPC classification number: H03K17/941 ,  H03K17/94 ,  H03K17/943 ,  H03K17/945 ,  H03K2217/94036 ,  H03K2217/94052 ,  H03K2217/94112

Abstract: A control circuit and a terminal are provided. The control circuit includes a detector, a current-voltage conversion circuit and a control signal generation circuit. The current output end of the detector is connected with the current input end of the current-voltage conversion circuit. The voltage output end of the current-voltage conversion circuit is connected with the voltage input end of the control signal generation circuit. The signal input end of the control signal generation circuit outputs a control signal. The detector detects a state of motion of a detected object and generates at least one current signal according to the state of motion of the detected object. The current-voltage conversion circuit converts the at least one current signal transmitted by the detector to at least one voltage signal. The control signal generation circuit generates the control signal based on a variation rule of the at least one voltage signal transmitted by the current-voltage conversion circuit and a preset control signal generation strategy, and output the control signal.

公开(公告)号：US20170068811A1

公开(公告)日：2017-03-09

申请号：US15123315

申请日：2014-05-19

Applicant: Sanechips Technology Co., Ltd.

Inventor： Wei LIU

IPC: G06F21/44 ,  G06F13/42 ,  G06F13/24 ,  G06F21/74 ,  G06F21/85

CPC classification number: G06F21/44 ,  G06F12/1441 ,  G06F12/1458 ,  G06F13/24 ,  G06F13/4282 ,  G06F21/74 ,  G06F21/85 ,  G06F2221/2105

Abstract: A method for secure access control based on an on-chip bus (advanced eXtensible interface, AXI) protocol is disclosed and comprises dividing a bus address space into more than one area, then determining the security attributes of each area; and, determining whether the security type of an access request, sent by a primary device, to access a target area matches the security attributes of said target area; if a match, sending said access request to a target secondary device. A device for secure access control based on the AXI protocol is also disclosed.

Abstract translation: 公开了一种基于片上总线（高级可扩展接口，AXI）协议的安全访问控制方法，包括将总线地址空间划分为多个区域，然后确定每个区域的安全属性; 并且确定由主设备发送的访问目标区域的访问请求的安全类型是否匹配所述目标区域的安全属性; 如果匹配，则将所述访问请求发送到目标辅助设备。 还公开了一种基于AXI协议的用于安全访问控制的设备。

公开(公告)号：US20160330122A1

公开(公告)日：2016-11-10

申请号：US15108374

申请日：2014-05-20

Applicant: SANECHIPS TECHNOLOGY CO., Ltd.

Inventor： Wei CHEN ,  Fanjin BU ,  Yongpeng YANG

IPC: H04L12/743 ,  H04L12/851

CPC classification number: H04L45/7453 ,  H04L45/7457 ,  H04L47/24

Abstract: The embodiments of disclosure disclose a method and device for forwarding data based on index allocation; the method includes that: the index allocation is performed, and a mapping relationship between a data forwarding priority and an index is established; according to the mapping relationship between the data forwarding priority and the index, high priority data of a data forwarding service is written into an address with a low index in a Ternary Content Addressable Memory (TCAM); and the data with the high priority of the data forwarding service is forwarded first.

Abstract translation: 公开的实施例公开了一种基于索引分配来转发数据的方法和设备; 该方法包括：执行索引分配，建立数据转发优先级和索引之间的映射关系; 根据数据转发优先级和索引之间的映射关系，将数据转发业务的高优先级数据写入三进制内容寻址存储器（TCAM）中具有低索引的地址; 首先转发具有高优先级的数据转发业务的数据。

公开(公告)号：US12293083B2

公开(公告)日：2025-05-06

申请号：US18018566

申请日：2021-07-05

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Yijun Zhou ,  Hengqi Liu ,  Jinlin Xu ,  Feng Zhou

IPC: G06F3/06

Abstract: The present disclosure provides a writing method, including: writing writing-table data into a corresponding main storage module; performing a calculation on writing-table data in each target main storage module by using a first predetermined algorithm to obtain an auxiliary value, for any target main storage module, the first predetermined algorithm being used for performing a calculation on writing-table data stored in the target main storage module and corresponding writing-table data stored in at least one main storage module other than the target main storage module, an inverse operation of the first predetermined algorithm being used for performing a calculation on any auxiliary value to obtain writing-table data participating in the calculation of the auxiliary value; and storing the auxiliary value into a corresponding auxiliary storage module. The present disclosure further provides a reading method, a computer readable storage medium, a processor chip and an electronic device.

公开(公告)号：US20250130940A1

公开(公告)日：2025-04-24

申请号：US19000081

申请日：2024-12-23

Applicant: SANECHIPS TECHNOLOGY CO, LTD.

Inventor： Min WANG ,  Jinlin XU ,  Yue WANG ,  Zihan TANG

IPC: G06F12/0802

Abstract: Embodiments of the present application relate to the technical field of network communication, and disclose a method and a device for caching a message, an electronic equipment and a storage medium. The method for caching the message includes: dividing a cache space into an N*N cache array, N being a natural number greater than zero, and each cache block in the cache array being in a same size; selecting a cache block for storing the message according to a size of the message to be stored and a number of free addresses of each cache block; and storing the message in a free address of a selected cache block.

公开(公告)号：US20250007927A1

公开(公告)日：2025-01-02

申请号：US18708249

申请日：2022-03-21

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Zhenfeng ZHANG ,  Hao SUN ,  Zhengxiang LI ,  Kun WANG ,  Sai WANG

IPC: H04L9/40

Abstract: Embodiments of the present disclosure relate to the field of communication transmission, and in particular, to a network anti-replay method and apparatus, an electronic device, and a storage medium. The network anti-replay method includes: according to a current packet number of a currently received data packet, determining a section to which the current packet number belongs in a replay window, with the replay window being divided into a plurality of sections, and each of the plurality of sections being configured to record packet numbers of L received data packets which belong to the section; and L being smaller than T, and T being a total number of packet numbers belonging to the section; and in a case where the current packet number is not coincident with packet numbers recorded in the determined section to which the current packet number belongs and the current packet number is not coincident with packet numbers of recently received N historical data packets, performing integrity authentication on the currently received data packet, with N being a natural number greater than 1.

公开(公告)号：US20250007525A1

公开(公告)日：2025-01-02

申请号：US18709161

申请日：2022-03-19

Applicant: SANECHIPS TECHNOLOGY CO.,LTD

Inventor： Licheng ZHU

IPC: H03L7/099 ,  H03L7/081 ,  H03L7/091

Abstract: A clock synchronization system and method are provided. The clock synchronization system includes: a pulse generation module, configured to receive an input first signal, perform sampling processing of the first signal to obtain a second signal, and generate a pulse signal according to the second signal; a voltage-controlled oscillator, configured to output a first output clock; the output frequency divider module, configured to perform frequency division on the first output clock, and synchronize, according to the pulse signal, the first output clock which has been subjected to the frequency division, so as to obtain a second output clock; and the synchronous output module, configured to receive the first output clock, the second output clock, the first signal, and the pulse signal, and perform synchronization processing on the first signal according to the first output clock, the second output clock and the pulse signal, so as to obtain a third signal.

公开(公告)号：US20250007481A1

公开(公告)日：2025-01-02

申请号：US18709090

申请日：2022-03-21

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Siyu LIN

IPC: H03G3/30 ,  H03G1/00 ,  H04B1/04

Abstract: Provided in the present disclosure is a variable gain amplifier, including: a voltage signal input end; a high level generation module including two high level signal output ends, and configured to convert a voltage signal input from the voltage signal input end into a first high level signal and a second high level signal; a switch signal conversion module including a high level signal input end, N digital signal input ends and N switch signal output ends, and configured to output, through corresponding switch signal output ends and under the control of signals input from the digital signal input ends, gain control signals associated with a signal output from the first high level signal output end; and an amplification module including an amplification unit and N stages of gain control units, where N is a positive integer not less than 1. Further provided is a transmitting apparatus.

公开(公告)号：US20240426883A1

公开(公告)日：2024-12-26

申请号：US18687909

申请日：2022-03-19

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Niuyi SUN ,  Dan YANG ,  Na MEI ,  Tuobei SUN

IPC: G01R27/08 ,  G01R1/20 ,  G01R31/26

Abstract: A circuit for acquiring a resistance value of a resistor includes: a working voltage node resistor Rb, a common ground voltage node resistor Rc, a reference node resistor Ra, a first interconnect parasitic resistor Rwire1, a second interconnect parasitic resistor Rwire2, an encapsulation network resistor Rnet, a first diode Dio_VDD, a Dio_Vss, and a Dio_die, wherein the working voltage node resistor Rb is respectively connected to one end of the Rwire1 and one end of the encapsulation network resistor Rnet. The other end of the Rwire1 is connected to a negative electrode of the Dio_VDD, and a positive electrode of the Dio_VDD is respectively connected to the Ra and a negative electrode of the Dio_Vss. A positive electrode of the Dio_VSS is respectively connected to the Rc and a negative electrode of the Dio_die via the Rwire2. A positive electrode of the Dio_die is connected to the other end of the Rnet.

公开(公告)号：US20240411555A1

公开(公告)日：2024-12-12

申请号：US18717053

申请日：2022-12-05

Applicant: SANECHIPS TECHNOLOGY CO., LTD.

Inventor： Hong LEI ,  Degen ZHEN ,  Tongqing WU ,  Dehui KONG ,  Ke XU

IPC: G06F9/30

Abstract: There are provided a vector operation method, a vector operator, an electronic device, and a computer-readable storage medium. The vector operation method includes: splitting a target vector operation to be performed to determine a plurality of basic operations in a predetermined execution order; sequentially generating, according to the predetermined execution order, a plurality of basic operation instructions corresponding to the plurality of basic operations; and sequentially executing, according to the predetermined execution order, the plurality of basic operation instructions on initial data to be subjected to the target vector operation, so as to implement the target vector operation on the initial data, wherein in two adjacent basic operations, to-be-calculated data for a latter basic operation is an operation result of a former basic operation.