公开(公告)号：US08234606B2

公开(公告)日：2012-07-31

申请号：US13080716

申请日：2011-04-06

Applicant: David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

Inventor： David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

IPC: G06F17/50 ,  H01L29/40

CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

Abstract translation: 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。

公开(公告)号：US08089135B2

公开(公告)日：2012-01-03

申请号：US12182585

申请日：2008-07-30

Applicant: Peter J. Lindgren ,  Anthony K. Stamper

Inventor： Peter J. Lindgren ,  Anthony K. Stamper

IPC: H01L21/02

CPC classification number: H01L23/5228 ,  G06F17/5068 ,  H01L23/5223 ,  H01L23/525 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Back-end-of-line (BEOL) wiring structures that include a passive element, such as a thin film resistor or a metal-insulator-metal capacitor, and multiple-height vias in a metallization level, as well as design structures for a radiofrequency integrated circuit. The wiring structures generally include a first metal-filled via in a dielectric layer having sidewalls that intersect the passive element and a second metal-filled via in the dielectric layer with sidewalls that do not intersect the passive element. The bottom of the first via includes a conductive layer that operates as an etch stop to prevent deepening of the sidewalls of the first via into a portion of the passive element when the second via is fully etched through the dielectric layer. A liner is applied to the layer of conductive material and the sidewalls of the first via, and the remaining space is filled with another conductive layer.

Abstract translation: 包括诸如薄膜电阻器或金属 - 绝缘体 - 金属电容器的无源元件以及金属化层级中的多个高通孔的后端行（BEOL）布线结构以及用于 射频集成电路。 布线结构通常包括具有与无源元件相交的侧壁的电介质层中的第一金属填充通孔和在电介质层中具有不与无源元件相交的侧壁的第二金属填充通孔。 第一通孔的底部包括作为蚀刻停止件工作的导电层，以防止当第二通孔被完全蚀刻通过电介质层时，将第一通孔的侧壁加深到无源元件的一部分中。 将衬垫施加到导电材料层和第一通孔的侧壁，并且剩余空间填充有另一导电层。

公开(公告)号：US20110185330A1

公开(公告)日：2011-07-28

申请号：US13080716

申请日：2011-04-06

Applicant: David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

Inventor： David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

IPC: G06F17/50

CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

Abstract translation: 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。

公开(公告)号：US20110177670A1

公开(公告)日：2011-07-21

申请号：US12690299

申请日：2010-01-20

Applicant: Russell T. Herrin ,  Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

Inventor： Russell T. Herrin ,  Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC: H01L21/71

CPC classification number: H01L21/76898 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing an integrated circuit structure forms a first opening in a substrate and lines the first opening with a protective liner. The method deposits a material into the first opening and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. The method removes the material from the first opening through the second opening in the protective material. The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

Abstract translation: 一种制造集成电路结构的方法在衬底中形成第一开口并且用保护性衬垫对第一开口进行排列。 该方法将材料沉积到第一开口中并在基底上形成保护材料。 保护材料包括工艺控制标记，并且包括在第一开口上方并对准第二开口的第二开口。 该方法通过保护材料中的第二开口从第一开口移除材料。 过程控制标记包括在保护材料内的仅部分延伸穿过保护材料的凹槽，使得在过程控制标记之下的基底的部分不受去除材料的过程的影响。

公开(公告)号：US20100032809A1

公开(公告)日：2010-02-11

申请号：US12188234

申请日：2008-08-08

Applicant: David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

Inventor： David S. Collins ,  Alvin Joseph ,  Peter J. Lindgren ,  Anthony K. Stamper ,  Kimball M. Watson

IPC: H01L23/538 ,  H01L21/768 ,  G06F17/50

CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

Abstract translation: 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。