公开(公告)号：US5824581A

公开(公告)日：1998-10-20

申请号：US738574

申请日：1996-10-28

Applicant: Horng-Huei Tseng

Inventor： Horng-Huei Tseng

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91

Abstract: An improved method for forming a dynamic random access memory (DRAM) capacitor includes forming a first dielectric layer on a substrate. The first dielectric layer is patterned and anisotropically etched to form a trench that defines a storage node area. A doped polysilicon layer is formed on the first dielectric layer and filling the trench. Next, a nitride layer is formed on the doped polysilicon layer and a dielectric stack is then formed over the nitride layer. The dielectric stack includes alternating layers of a second dielectric material and a third dielectric material, each dielectric material having a different etch rate. The dielectric stack is patterned and anisotropically etched to form a laminated pillar. The pillar is then isotropically etched to form recessed cavities in a sidewall of the pillar. Portions of the nitride layer are then removed using the pillar as a mask, and a doped polysilicon layer is conformally formed over the pillar so as to fill the recessed cavities. Afterwards, portions of the doped polysilicon layer are removed to expose the upper surface of the pillar, and the pillar is removed while leaving the residual doped polysilicon layer intact, thereby forming an electrode of the capacitor of the DRAM cell.

Abstract translation: 用于形成动态随机存取存储器（DRAM）电容器的改进方法包括在衬底上形成第一介电层。 第一介电层被图案化并各向异性蚀刻以形成限定存储节点区域的沟槽。 掺杂多晶硅层形成在第一介电层上并填充沟槽。 接下来，在掺杂多晶硅层上形成氮化物层，然后在氮化物层上形成电介质叠层。 电介质堆叠包括第二电介质材料和第三电介质材料的交替层，每个电介质材料具有不同的蚀刻速率。 对电介质堆叠进行图案化和各向异性蚀刻以形成层压柱。 然后将柱子进行各向同性蚀刻，以在柱的侧壁中形成凹陷的空腔。 然后使用柱作为掩模去除氮化物层的一部分，并且在柱上共形形成掺杂多晶硅层以填充凹陷腔。 然后，去除掺杂多晶硅层的部分以暴露柱的上表面，并且移除柱，同时使残留的掺杂多晶硅层保持不变，从而形成DRAM单元的电容器的电极。

公开(公告)号：US5807775A

公开(公告)日：1998-09-15

申请号：US668713

申请日：1996-06-24

Applicant: Horng-Huei Tseng

Inventor： Horng-Huei Tseng

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for manufacturing a double walled cylindrical stacked capacitor for a DRAM using only one photo mask is provided. An insulating layer having a contact opening is formed over a transistor. A first conductive layer is then formed over the insulating layer. The first conductive layer is patterned forming a central spine over the contact opening and portions of the first conductive layer are left covering the insulation layer. Dielectric spacers are formed on the sidewall of the central spine. The remaining portions of the first conductive layer over the first insulating layer are removed and upper portions of the central spine are removed forming a conductive base. Inner and outer conductive walls are formed on the sidewalls of the dielectric spacers thereby forming a double walled bottom electrode. The dielectric spacers are removed. A capacitor dielectric layer and a top electrode are formed over the bottom electrode forming the capacitor. The invention uses sidewall spacers and selective etching techniques to forms a low cost, simple to manufacture, high capacitance capacitor and DRAM cell.

Abstract translation: 提供了仅使用一个光掩模制造用于DRAM的双壁圆柱形堆叠电容器的方法。 在晶体管上形成具有接触开口的绝缘层。 然后在绝缘层上形成第一导电层。 第一导电层被图案化以在接触开口上形成中心脊，并且第一导电层的部分被覆盖绝缘层。 电介质垫片形成在中心脊的侧壁上。 除去第一绝缘层上的第一导电层的剩余部分，去除形成导电基底的中心脊的上部。 内导电壁和外导电壁形成在介电间隔物的侧壁上，从而形成双壁底电极。 去除电介质垫片。 在形成电容器的底部电极上形成电容器电介质层和顶部电极。 本发明使用侧壁间隔物和选择性蚀刻技术来形成低成本，易于制造的高容量电容器和DRAM单元。

公开(公告)号：US5795806A

公开(公告)日：1998-08-18

申请号：US835576

申请日：1997-04-09

Applicant: Horng-Huei Tseng

Inventor： Horng-Huei Tseng

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  Y10S438/964

Abstract: A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a grated top surface topography for a polysilicon storage node electrode. The grated top surface topography is obtained by using a composite spot structure, of silicon oxide on small diameter, HSG polysilicon spots, as a mask for an anisotropic dry etch procedure, used to define lower features in an underlying polysilicon layer. The raised features of the grated top surface topography of the polysilicon storage node electrode, is comprised of the masking, small diameter, HSG polysilicon spots, on regions of the unetched polysilicon layer.

Abstract translation: 已经开发了用于高密度DRAM设计的STC结构的创建方法。 该过程包括为多晶硅存储节点电极创建格栅的顶表面形貌。 通过使用小直径上的氧化硅，HSG多晶硅斑点的复合点结构作为用于各向异性干法蚀刻程序的掩模，用于限定下面的多晶硅层中的较低特征来获得磨碎的顶表面形貌。 多晶硅存储节点电极的磨碎的顶表面形貌的凸起特征包括在未蚀刻的多晶硅层的区域上的掩蔽，小直径的HSG多晶硅斑点。

公开(公告)号：US5793077A

公开(公告)日：1998-08-11

申请号：US709895

申请日：1996-09-09

Applicant: Horng-Huei Tseng

Inventor： Horng-Huei Tseng

IPC: H01L21/02 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/72

CPC classification number: H01L27/10861 ,  H01L28/82 ,  H01L29/66181

Abstract: A method, and resultant structure, is described for fabricating a DRAM trench capacitor with a single pillar recessed below the level of the top surface of the silicon substrate in which it is formed. First and second insulating layers are formed over the silicon substrate, and patterned to form an opening to the silicon substrate. A portion of the silicon substrate is removed in the region defined by the opening, whereby a first trench is formed. Sidewall spacers are formed along the sides of the first trench from a third insulating layer. A first pillar is formed after depositing a first conductive layer between the sidewall spacers and over the trench and removing the first conductive layer except within the first trench. The sidewall spacers are removed. A portion of the silicon substrate in the first trench is removed that is not vertically masked by the pillar, and simultaneously a portion top of the pillar is removed, whereby a second trench and second pillar are formed at a greater depth in the silicon substrate. The remainder of the second insulating layer is also removed. A capacitor dielectric is formed in the second trench over the second pillar. A second conducting layer is formed over the dielectric layer and removed in the region outside of the trench to form the top capacitor electrode.

Abstract translation: 描述了一种用于制造DRAM沟槽电容器的方法和结果，该DRAM沟槽电容器具有在其所形成的硅衬底的顶表面的下方凹陷的单个柱体。 第一和第二绝缘层形成在硅衬底上，并被图案化以形成到硅衬底的开口。 在由开口限定的区域中去除硅衬底的一部分，从而形成第一沟槽。 从第三绝缘层沿着第一沟槽的侧面形成侧壁间隔物。 在第一导电层沉积在侧壁间隔物之间​​并在沟槽之上并除去第一沟槽以外的第一导电层时形成第一柱。 去除侧壁间隔物。 第一沟槽中的硅衬底的一部分被去除而不被柱垂直掩蔽，同时去除柱的一部分顶部，从而在硅衬底中形成更大深度的第二沟槽和第二柱。 第二绝缘层的其余部分也被去除。 在第二支柱上的第二沟槽中形成电容器电介质。 在电介质层上形成第二导电层，并在沟槽外部的区域中去除第二导电层以形成顶部电容器电极。

公开(公告)号：US5792693A

公开(公告)日：1998-08-11

申请号：US813721

申请日：1997-03-07

Applicant: Horng-Huei Tseng

Inventor： Horng-Huei Tseng

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for manufacturing an array of stacked capacitors with increased capacitance on a dynamic random access memory (DRAM) device was achieved. The invention uses a thermal oxidation and anisotropic plasma etch to form sidewall spacers in a recess or trench in a first polysilicon layer over the capacitor node contacts to the FETs. The recesses within the sidewall spacers are then filled with a second polysilicon layer and chem/mech polished back to form studs. The sidewall spacers are then selectively removed by a wet etch and a patterned second photoresist layer is used to pattern the first polysilicon layer into an array of capacitor bottom electrodes with vertical portions that increase the surface area. An interelectrode dielectric layer is formed on the bottom electrodes and a third polysilicon layer is deposited and patterned to form the top electrodes and to complete the array of stacked capacitors on the DRAM device.

Abstract translation: 实现了在动态随机存取存储器（DRAM）器件上制造具有增加的电容的堆叠电容器阵列的方法。 本发明使用热氧化和各向异性等离子体蚀刻在电容器节点与FET接触的第一多晶硅层的凹槽或沟槽中形成侧壁间隔物。 然后在侧壁间隔物内的凹陷部分填充有第二多晶硅层，并且抛光后的化学/机械结构以形成螺柱。 然后通过湿蚀刻选择性地去除侧壁间隔物，并且使用图案化的第二光致抗蚀剂层将第一多晶硅层图案化成具有增加表面积的垂直部分的电容器底部电极的阵列。 在底部电极上形成电极间电介质层，并且沉积和图案化第三多晶硅层以形成顶部电极并在DRAM器件上完成叠层电容器阵列。

公开(公告)号：US5792688A

公开(公告)日：1998-08-11

申请号：US746061

申请日：1996-11-06

Applicant: Horng-Huei Tseng

Inventor： Horng-Huei Tseng

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a lower, or storage node electrode, for the STC structure, consisting of a flat, polysilicon plug, contacting an underlying transistor region, and of an upper polysilicon shape, comprised of polysilicon columns, extending between about 2500 to 6000 Angstroms, above the top surface of the flat, polysilicon plug. The flat, polysilicon plug is formed via creation of a capacitor contact hole, in an insulator layer, followed by polysilicon deposition, and RIE etch back, creating the flat, polysilicon plug, recessed in a lower portion of the capacitor contact hole. Another polysilicon deposition, and anisotropic RIE procedure, results in the formation of polysilicon columns, on the sides of the upper portion of the capacitor contact hole. Removal of insulator layers expose the storage node electrode, comprised of polysilicon columns, overlying, and extending above, the underlying flat, polysilicon plug.

Abstract translation: 已经开发了用于高密度DRAM设计的STC结构的创建方法。 该过程包括为STC结构创建一个下层或存储节点电极，由一个平坦的多晶硅插塞，一个底层晶体管区域和一个上部多晶硅形状组成，上部多晶硅形状由多晶硅柱组成，延伸约2500至6000 埃，平顶上表面，多晶硅塞。 平坦的多晶硅插塞通过在绝缘体层中产生电容器接触孔，随后进行多晶硅沉积而形成，并且RIE蚀回，从而产生凹入电容器接触孔的下部的平坦的多晶硅插塞。 另外的多晶硅沉积和各向异性RIE程序导致在电容器接触孔的上部侧面上形成多晶硅柱。 去除绝缘体层将覆盖并延伸到下面的平坦多晶硅插塞的多晶硅柱的存储节点电极暴露。

公开(公告)号：US5766994A

公开(公告)日：1998-06-16

申请号：US827816

申请日：1997-04-11

Applicant: Horng-Huei Tseng

Inventor： Horng-Huei Tseng

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91

Abstract: A method for making an array of DRAM cells having increased capacitance was achieved. The method forms a planar insulating layer in which are etched capacitor node contact openings to each FET in an array of cells. A first polysilicon layer is deposited to fill the node contact openings and provide a polysilicon planar surface on the insulating layer. A multilayer of alternate layers of a traditional LPCVD silicon oxide and O.sub.3 /TEOS silicon oxide is deposited and patterned having openings aligned over the capacitor node contacts where the capacitors are required. The multilayer is then etched in HF to partially etch and recess the faster etching O.sub.3 /TEOS oxide, forming grooves in the sidewalls of the multilayer structure. A second polysilicon layer is then conformally deposited, etched back and the exposed multilayer structure is selectively removed in HF to leave free-standing bottom electrodes having sidewall spacers and a center pillar that replicate the grooves in the multilayer, thereby providing increased surface area. An interelectrode dielectric layer is formed on the bottom electrodes and a third polysilicon layer is deposited and patterned to form the top electrodes and to complete the array of stacked capacitors on the DRAM device.

Abstract translation: 实现了具有增加的电容的DRAM单元阵列的制造方法。 该方法形成平面绝缘层，其中在单元阵列中的每个FET蚀刻电容器节点接触开口。 沉积第一多晶硅层以填充节点接触开口并在绝缘层上提供多晶硅平坦表面。 传统的LPCVD氧化硅和O 3 / TEOS氧化硅的交替层的多层被沉积和图案化，其具有在需要电容器的电容器节点触点上对齐的开口。 然后在HF中蚀刻多层以部分蚀刻和凹陷更快蚀刻的O 3 / TEOS氧化物，在多层结构的侧壁中形成凹槽。 然后共形沉积第二多晶硅层，回蚀刻，并且在HF中选择性地除去暴露的多层结构以留下具有侧壁间隔物的独立底部电极和复制多层中的凹槽的中心柱，从而提供增加的表面积。 在底部电极上形成电极间电介质层，并且沉积和图案化第三多晶硅层以形成顶部电极并在DRAM器件上完成叠层电容器阵列。

公开(公告)号：US5763304A

公开(公告)日：1998-06-09

申请号：US726911

申请日：1996-10-07

Applicant: Horng-Huei Tseng

Inventor： Horng-Huei Tseng

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/91

Abstract: A method of forming a capacitor on a semiconductor substrate includes forming a first oxide layer on the semiconductor substrate. A contact hole is then formed in the first oxide layer. A first conductive layer is formed on the first oxide layer and in the contact hole. Then the first conductive layer is etched back to the surface of said first oxide layer. A trench is formed in the first dielectric layer aligned with the first conductive layer, with the upper portion of the first conductive layer extending upwards from the bottom surface of the trench. A second conductive layer is conformally deposited on the first conductive layer and the first oxide layer. A second oxide layer is formed on the second conductive layer, filling the trench. A chemical mechanical polishing (CMP) process is then performed to remove the upper portions of the first and second oxide layers and the first and second conductive layers. The lower portions of the first and second oxide layers are removed by using a highly selective etching process. The resulting polysilicon structure serves as a bottom storage node of the capacitor. A dielectric film is formed on the first conductive layer and the second conductive layer. A third conductive layer is formed over the dielectric film to form the top storage node of the capacitor.

Abstract translation: 在半导体衬底上形成电容器的方法包括在半导体衬底上形成第一氧化物层。 然后在第一氧化物层中形成接触孔。 在第一氧化物层和接触孔中形成第一导电层。 然后将第一导电层回蚀刻到所述第一氧化物层的表面。 在与第一导电层对准的第一电介质层中形成沟槽，第一导电层的上部从沟槽的底表面向上延伸。 第二导电层共形沉积在第一导电层和第一氧化物层上。 在第二导电层上形成第二氧化物层，填充沟槽。 然后执行化学机械抛光（CMP）工艺以除去第一和第二氧化物层以及第一和第二导电层的上部。 通过使用高选择性蚀刻工艺来去除第一和第二氧化物层的下部。 所得的多晶硅结构用作电容器的底部存储节点。 在第一导电层和第二导电层上形成电介质膜。 在电介质膜上形成第三导电层以形成电容器的顶部存储节点。

公开(公告)号：US5759894A

公开(公告)日：1998-06-02

申请号：US808338

申请日：1997-02-28

Applicant: Horng-Huei Tseng ,  Chih-Yuan Lu

Inventor： Horng-Huei Tseng ,  Chih-Yuan Lu

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/92

Abstract: A method for forming a DRAM capacitor using HSG-Si includes forming a dielectric layer over a substrate. A portion of the dielectric layer is removed to expose a contact area on the substrate. A polysilicon layer is then formed over the dielectric layer and in the first trench. Then, a hemispherical-grained silicon (HSG-Si) layer is formed on the polysilicon layer using an initial phase HSG-Si process, thereby forming a large number of silicon grains on the polysilicon layer. Next, nitrogen atoms are implanted into the polysilicon layer using the HSG-Si layer as a mask to form nitrogen regions in the polysilicon layer. The HSG-Si layer is then removed and the polysilicon layer is thermally oxidized. The nitrogen regions function as an anti-oxidation mask so that polysilicon-oxide regions are formed between the nitrogen regions in the polysilicon layer. Afterwards, an etching process is performed using the polysilicon-oxide regions as a mask so that the nitrogen regions and portions of the polysilicon layer beneath the nitrogen regions are removed. This etching step forms second trenches in the polysilicon layer between the polysilicon-oxide regions, which are subsequently removed. After removing the polysilicon-oxide regions, the polysilicon layer is patterned and etched to form a bottom electrode of the capacitor of the dynamic random access memory. The capacitor dielectric and the top electrode of the capacitor are then formed using conventional methods.

Abstract translation: 使用HSG-Si形成DRAM电容器的方法包括在衬底上形成电介质层。 去除介电层的一部分以露出衬底上的接触区域。 然后在电介质层上和第一沟槽中形成多晶硅层。 然后，使用初始相HSG-Si工艺在多晶硅层上形成半球状硅（HSG-Si）层，从而在多晶硅层上形成大量的硅晶粒。 接下来，使用HSG-Si层作为掩模将氮原子注入到多晶硅层中，以在多晶硅层中形成氮区。 然后去除HSG-Si层，并且多晶硅层被热氧化。 氮区域用作抗氧化掩模，使得在多晶硅层中的氮区域之间形成多晶氧化物区域。 然后，使用多晶硅氧化物区域作为掩模进行蚀刻处理，使得氮区域和氮区域下方的多晶硅层的部分被去除。 该蚀刻步骤在多晶硅层之间形成第二沟槽，该多晶硅层随后被去除。 在去除多晶硅氧化物区域之后，对多晶硅层进行图案化和蚀刻以形成动态随机存取存储器的电容器的底部电极。 然后使用常规方法形成电容器电介质和电容器的顶部电极。

公开(公告)号：US5759891A

公开(公告)日：1998-06-02

申请号：US814135

申请日：1997-03-10

Applicant: Horng-Huei Tseng

Inventor： Horng-Huei Tseng

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L21/32139 ,  H01L27/10817 ,  H01L28/92

Abstract: A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a saw-toothed topography for the top surface of a polysilicon storage node electrode. The saw-toothed topography is obtained by placing intrinsic HSG polysilicon spots on an underlying doped polysilicon layer. An anisotropic RIE procedure, using SF.sub.6, as an etchant, removes doped polysilicon at a faster rate then the removal rate of the masking intrinsic HSG polysilicon spots, resulting in a saw-toothed topography in the polysilicon storage node electrode, comprised of raised features of HSG polysilicon spots, on unetched doped polysilicon, and lower features of etched, doped polysilicon. The saw-toothed topography, increases the surface area of the polysilicon storage node electrode, thus furnishing capacitance increases.

Abstract translation: 已经开发了用于高密度DRAM设计的STC结构的创建方法。 该过程包括为多晶硅存储节点电极的顶表面创建锯齿状的形貌。 通过将固有的HSG多晶硅斑点放置在下面的掺杂多晶硅层上来获得锯齿状的形貌。 使用SF6作为蚀刻剂的各向异性RIE程序以更快的速率去除掺杂多晶硅，然后掩蔽本征HSG多晶硅斑点的去除速率，导致多晶硅存储节点电极中的锯齿形地貌，包括 HSG多晶硅斑点，未蚀刻掺杂多晶硅，以及蚀刻掺杂多晶硅的较低特征。 锯齿形地形增加了多晶硅储存节点电极的表面积，从而提高了电容量。