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公开(公告)号：US11599360B2
公开(公告)日：2023-03-07
申请号：US17242374
申请日：2021-04-28
发明人： David Sherwood , Terry A. Higbee
摘要： A synaptic coprocessor may include a memory configured to store a plurality of Very Long Data Words, each as a test Very Long Data Word (VLDW) having a length in the range of about one thousand bits to one million or more bits and containing encoded information that is distributed across the length of the VLDW. A processor generates search terms and a processing logic unit receives a test VLDW from the memory, receives a search term from the processor, and computes a Boolean inner product between the search term and the test VLDW read from memory indicative of the measure of similarity between the test VLDW and the search term. Optionally, buffers within logic circuits of processing pipelines may receive the test VLDWs.
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公开(公告)号：US11593070B2
公开(公告)日：2023-02-28
申请号：US16814479
申请日：2020-03-10
发明人： Rie Sato , Koichi Mizushima
IPC分类号： G06F7/57 , G06N3/04 , G06N3/063 , G11C11/407 , H01L27/108 , G06N3/049
摘要： According to one embodiment, an arithmetic device includes an arithmetic circuit. The arithmetic circuit includes a memory part including a plurality of memory regions, and an arithmetic part. One of the memory regions includes a capacitance including a first terminal, and a first electrical circuit electrically connected to the first terminal and configured to output a voltage signal corresponding to a potential of the first terminal.
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公开(公告)号：US20230025291A1
公开(公告)日：2023-01-26
申请号：US17960477
申请日：2022-10-05
摘要： Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.
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公开(公告)号：US11561795B2
公开(公告)日：2023-01-24
申请号：US16834833
申请日：2020-03-30
申请人： Arm Limited
发明人： Jens Olson , John Wakefield Brothers, III , Jared Corey Smolens , Chi-wen Cheng , Daren Croxford , Sharjeel Saeed , Dominic Hugo Symes
摘要： Herein described is a method of operating an accumulation process in a data processing apparatus. The accumulation process comprises a plurality of accumulations which output a respective plurality of accumulated values, each based on a stored value and a computed value generated by a data processing operation. The method comprises storing a first accumulated value, the first accumulated value being one of said plurality of accumulated values, into a first storage device comprising a plurality of single-bit storage elements; determining that a predetermined trigger has been satisfied with respect to the accumulation process; and in response to the determining, storing at least a portion of a second accumulated value, the second accumulated value being one of said plurality of accumulated values, into a second storage device.
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公开(公告)号：US20230005990A1
公开(公告)日：2023-01-05
申请号：US17784652
申请日：2020-07-23
发明人： Ling Shen , Yu Jiang , Huijie Yan , Zhifang Li , Linmei Dong , Jiebin Duan , Jianxin Wen
摘要： The present invention disclosures a memory array structure, comprising an array composed of multiple memory devices arranged in rows and columns, each of the rows is set with a row leading-out wire, and each of the columns is set with a column leading-out wire, memory devices are correspondingly positioned at intersection points of each row leading-out wire and each column leading-out wire; wherein, the first terminal of each of the memory devices is individually connected to the row leading-out wire of the same row, and the second terminal of each of the memory devices is connected to a first terminal of a switch in the same column, the second terminal of the switch is connected to the column leading-out wire of the same column; wherein, each of the rows is set with one to multiple the switches, and the first terminal of each of the switches is connected to one to all of the second terminals of the memory devices in the same column. The advantage of the present invention is that the corresponding analog currents output of input signals of different specified rows according to multiply-accumulate operation requirements of each of the columns can be obtained simultaneously, thus multiply-accumulate operations of different input signals of different scales can be performed, which greatly improves operation speed and using efficiency of the array.
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公开(公告)号：US20220405601A1
公开(公告)日：2022-12-22
申请号：US17349508
申请日：2021-06-16
发明人： Alon MARCU , Ariel NAVON , Judah Gamliel HAHN , Shay BENISTY , Eran SHARON , Karin INBAR
摘要： A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.
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公开(公告)号：US20220350640A1
公开(公告)日：2022-11-03
申请号：US17242353
申请日：2021-04-28
发明人： Rajat Rao
摘要： Embodiments are directed to selecting a multiplication operation to be scheduled in a first stage of an execution schedule, the multiplication operation meeting a first condition of having no dependency. An addition/subtraction operation is selected to be scheduled in the first stage of the execution schedule responsive to meeting the first condition. A process is performed which includes selecting another multiplication operation to be scheduled in a next stage of the execution schedule responsive to meeting the first condition or a second condition, the second condition including having a dependency that is fulfilled by a previous stage. The process includes selecting another addition/subtraction operation to be scheduled in the next stage of the execution schedule responsive to meeting the first or second condition, and repeating the process until each operation has been scheduled in the execution schedule, where the execution schedule is configured for execution by an arithmetic logic unit.
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公开(公告)号：US11474788B2
公开(公告)日：2022-10-18
申请号：US16890870
申请日：2020-06-02
发明人： Nitin Chawla , Tanmoy Roy , Anuj Grover , Giuseppe Desoli
摘要： A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
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公开(公告)号：US11461075B2
公开(公告)日：2022-10-04
申请号：US17004228
申请日：2020-08-27
摘要： According to an embodiment, an arithmetic device includes a comparator, M cross switches, and M coefficient circuits. The comparator compares a first voltage generated at a first comparison terminal and a second voltage generated at a second comparison terminal. The M cross switches are provided corresponding to the M input signals. The M coefficient circuits are provided corresponding to the M coefficients, and each includes a first constant current source and a second constant current source. Each of the M cross switches performs switching between a straight state and a reverse state. In each of the M coefficient circuits, the first constant current source is connected between a positive output terminal of the corresponding coefficient circuit and a reference potential, and the second constant current source is connected between a negative output terminal of the corresponding coefficient circuit and the reference potential.
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公开(公告)号：US20220292049A1
公开(公告)日：2022-09-15
申请号：US17751487
申请日：2022-05-23
IPC分类号： G06F15/173 , G06N3/08 , G06F17/16 , G06F7/57 , G06F7/533 , G06F7/544 , G06F9/38 , G06F13/16 , G06F17/15
摘要： A system for calculating. A scratch memory is connected to a plurality of configurable processing elements by a communication fabric including a plurality of configurable nodes. The scratch memory sends out a plurality of streams of data words. Each data word is either a configuration word used to set the configuration of a node or of a processing element, or a data word carrying an operand or a result of a calculation. Each processing element performs operations according to its current configuration and returns the results to the communication fabric, which conveys them back to the scratch memory.
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