公开(公告)号：US06496193B1

公开(公告)日：2002-12-17

申请号：US09475706

申请日：1999-12-30

Applicant: Prasoonkumar B. Surti ,  Aditya Sreenivas

Inventor： Prasoonkumar B. Surti ,  Aditya Sreenivas

IPC: G06T1140

CPC classification number: G06T15/04 ,  G06T11/40

Abstract: An apparatus for loading texture data into a tiled memory includes state machine logic to generate a sequence of addresses for writing a cacheline of texture data into the tiled memory according to Y-major tiling. The cacheline comprises quadwords (QWs) 0-3, wherein the sequence corresponds to an ordering of the QWs 0-3, ordered as either: (a) QW0, QW1, QW2, QW3; (b) QW1, QW0, QW3, QW2; (c) QW2, QW3, QW0, QW1; or (d) QW3, QW2, QW1, QW0, depending upon a starting address.

Abstract translation: 用于将纹理数据加载到平铺存储器中的装置包括状态机逻辑，用于根据Y-主平铺生成用于将纹理数据的高速缓存线写入到平铺存储器中的地址序列。 高速缓存线包括四字（QW）0-3，其中该序列对应于QWs 0-3的顺序，其顺序为：（a）QW0，QW1，QW2，QW3; （b）QW1，QW0，QW3，QW2; （c）QW2，QW3，QW0，QW1; 或（d）QW3，QW2，QW1，QW0，这取决于起始地址。

公开(公告)号：US06362826B1

公开(公告)日：2002-03-26

申请号：US09231609

申请日：1999-01-15

Applicant: Peter Doyle ,  Aditya Sreenivas

Inventor： Peter Doyle ,  Aditya Sreenivas

IPC: G06F1316

CPC classification number: G09G5/363 ,  G09G5/393 ,  G09G2360/122

Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.

Abstract translation: 提供了一种用于实现动态显示存储器的方法和装置。 适于中央处理器和存储器之间插入的存储器控​​制中心包括图形存储器控制部件。 图形存储器控制组件确定中央处理器访问的操作数是否是图形操作数。 如果是这样，则图形存储器控制部件将由中央处理器提供的虚拟地址转换成适合于将图形操作数定位在存储器中的系统地址。 在一个实施例中，图形控制组件在存储器中维护图形转换表，并利用图形转换表将虚拟地址转换成系统地址。 此外，在一个实施例中，图形控制部件重新排列图形操作数的地址以优化图形设备的性能存储器访问。

公开(公告)号：US6141023A

公开(公告)日：2000-10-31

申请号：US16795

申请日：1998-01-30

Applicant: Kim A. Meinerth ,  Aditya Sreenivas ,  Krishnan Sreenivas ,  John A. Carey

Inventor： Kim A. Meinerth ,  Aditya Sreenivas ,  Krishnan Sreenivas ,  John A. Carey

IPC: G09G5/00 ,  G09G5/36 ,  G06F12/00

CPC classification number: G09G5/363

Abstract: An apparatus for an efficient display flip is disclosed. The apparatus has a computer readable medium having a graphics driver. The execution of the graphics driver is configured to generate instructions for checking status of a graphics device to determine whether the graphics device is ready to display a next frame data on a display device. The graphics device is coupled to a system memory. The graphics device is configured to forwarding a display flip status to the system memory for access by the graphics driver in response to the instructions.

Abstract translation: 公开了一种用于高效显示翻转的装置。 该装置具有具有图形驱动器的计算机可读介质。 图形驱动器的执行被配置为生成用于检查图形设备的状态的指令，以确定图形设备是否准备好在显示设备上显示下一帧数据。 图形设备耦合到系统存储器。 图形设备被配置为将显示翻转状态转发到系统存储器以供图形驱动程序响应于指令进行访问。

公开(公告)号：US6026451A

公开(公告)日：2000-02-15

申请号：US996303

申请日：1997-12-22

Applicant: Aditya Sreenivas

Inventor： Aditya Sreenivas

IPC: G06F5/10 ,  G06F5/14 ,  G06F13/364 ,  G06F13/14

CPC classification number: G06F5/14 ,  G06F13/364

Abstract: In one aspect of the present invention, a method is provided for controlling dispatches of requested data packets. The method includes sending information on each of the requested data packets to a request buffer, generating at least one size signal from the information sent on each of the requested data packets, and generating an available space signal. The size signal corresponds to a size of one of the requested data packets that may be received next. The available space signal corresponds to space available in a data buffer. The data buffer receives the requested data packets. The method also includes comparing the size signal to the available space signal and asserting a data buffer full signal in response to the size signal being greater than the available space signal.

Abstract translation: 在本发明的一个方面，提供一种用于控制所请求的数据分组的分派的方法。 该方法包括将每个所请求的数据分组的信息发送到请求缓冲器，从在每个所请求的数据分组上发送的信息生成至少一个大小的信号，并产生可用的空间信号。 尺寸信号对应于接下来可以接收的所请求的数据分组之一的大小。 可用空间信号对应于数据缓冲区中可用的空间。 数据缓冲器接收请求的数据包。 该方法还包括将尺寸信号与可用空间信号进行比较，并根据尺寸信号大于可用空间信号来确定数据缓冲器满信号。

公开(公告)号：US07612780B2

公开(公告)日：2009-11-03

申请号：US11784342

申请日：2007-04-06

Applicant: David E Freker ,  Aditya Sreenivas ,  Zohar Bogin ,  Anoop Mukker ,  Tuong Trieu

Inventor： David E Freker ,  Aditya Sreenivas ,  Zohar Bogin ,  Anoop Mukker ,  Tuong Trieu

IPC: G09G5/399 ,  G06F13/00 ,  G09G5/39

CPC classification number: G06F13/1684

Abstract: Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Abstract translation: 本发明的实施例涉及使用双通道存储器件的第一通道访问第一对相邻数据块; 并且使用所述存储器件的第二通道同时访问第二对相邻数据块，所述第二对与所述第一对间隔开预定间隔。

公开(公告)号：US07164427B2

公开(公告)日：2007-01-16

申请号：US11096343

申请日：2005-03-31

Applicant: Peter L. Doyle ,  Aditya Sreenivas

Inventor： Peter L. Doyle ,  Aditya Sreenivas

IPC: G06F12/02 ,  G09G5/36

CPC classification number: G06F3/1431 ,  G06T15/005

Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.

Abstract translation: 一种同时呈现独立图像以在一个或多个显示设备上显示的方法，装置和系统。 在一个实施例中，图形呈现引擎同时呈现独立图像以在多个显示设备上显示。 时间分配器在呈现的每个独立图像之间对并行使用图形渲染引擎进行仲裁。

公开(公告)号：US07051172B2

公开(公告)日：2006-05-23

申请号：US10932395

申请日：2004-09-01

Applicant: Josh B. Mastronarde ,  Aditya Sreenivas ,  Thomas A. Piazza

Inventor： Josh B. Mastronarde ,  Aditya Sreenivas ,  Thomas A. Piazza

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F13/161 ,  G06F13/18

Abstract: Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

公开(公告)号：US06995773B2

公开(公告)日：2006-02-07

申请号：US10861589

申请日：2004-06-03

Applicant: Peter L. Doyle ,  Aditya Sreenivas

Inventor： Peter L. Doyle ,  Aditya Sreenivas

IPC: G09G5/36

CPC classification number: G06T1/60 ,  G06T15/04

Abstract: The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.

Abstract translation: 本发明通过在分箱和渲染阶段之间提供bin存储器的自动管理来优化区域渲染期间的图形性能。 本发明的实施例提供了一种机制，通过该机制，虚拟机和渲染器自动共享物理存储器页面池，以便构建bin缓冲器并在渲染后使用它们。 这样做的方式是，可以将多个分箱的场景同时排队，除非在特殊情况下不需要软件干预。 因此消除了对区域渲染bin缓冲存储器的软件管理的需要。 用于分档和渲染的多个场景也可以排队等待，无需软件干预。

公开(公告)号：US06954208B2

公开(公告)日：2005-10-11

申请号：US10844094

申请日：2004-05-11

Applicant: Peter L. Doyle ,  Aditya Sreenivas

Inventor： Peter L. Doyle ,  Aditya Sreenivas

IPC: G06T1/60 ,  G06F13/00 ,  G06T15/40 ,  G06T17/10

CPC classification number: G06T1/60 ,  G06T15/405

Abstract: A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.

Abstract translation: 一种深度写入禁止装置和方法，用于控制从区域渲染系统中的深度缓存到相应的深度缓冲区的撤离，例如深度值。 当深度写入禁止电路被使能时，防止从深度缓存（通常在渲染下一个区域期间发生）到深度缓冲区的驱逐。 特别地，一旦深度缓冲器被初始化（即清除）到场景开始处的恒定值，则不需要读取深度缓冲器。 深度缓存处理每个区域内的中间深度读取和写入。 由于在呈现场景后不需要内存驻留深度缓冲区，因此不需要写入。 因此，在每个区域呈现之后，区域的最终深度值因此可被丢弃（即，而不是写入深度缓冲区）。

公开(公告)号：US20050212805A1

公开(公告)日：2005-09-29

申请号：US11045018

申请日：2005-01-26

Applicant: Peter Doyle ,  Aditya Sreenivas

Inventor： Peter Doyle ,  Aditya Sreenivas

IPC: G06F15/16 ,  G06T1/00 ,  G06T1/20

CPC classification number: G06T1/20

Abstract: An image is rendered by dividing the image into chunks, rendering the chunks in one of at least two devices, and determining which of the devices renders each one of at least some of the chunks based on at least one device's progress in the rendering of other chunks.