公开(公告)号：US20190035917A1

公开(公告)日：2019-01-31

申请号：US15812350

申请日：2017-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Lun Cheng ,  Li-Shyue Lai ,  Ching-Wei Tsai ,  Kai-Chieh Yang

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L21/311

Abstract: Examples of an integrated circuit with a gate stack and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a workpiece that includes: a pair of sidewall spacers disposed over a channel region, a gate dielectric disposed on the channel region and extending along a vertical surface of a first spacer of the pair of sidewall spacers, and a capping layer disposed on the high-k gate dielectric and extending along the vertical surface. A shaping feature is formed on the capping layer and the high-k gate dielectric. A first portion of the high-k gate dielectric and a first portion of the capping layer disposed between the shaping feature and the first spacer are removed to leave a second portion of the high-k gate dielectric and a second portion of the capping layer extending along the vertical surface.