公开(公告)号：US11361989B2

公开(公告)日：2022-06-14

申请号：US16788057

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chin Lee ,  Shao-Kuan Lee ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/02

Abstract: A method and structure for forming a barrier-free interconnect layer includes patterning a metal layer disposed over a substrate to form a patterned metal layer including one or more trenches. In some embodiments, the method further includes selectively depositing a barrier layer on metal surfaces of the patterned metal layer within the one or more trenches. In some examples, and after selectively depositing the barrier layer, a dielectric layer is deposited within the one or more trenches. Thereafter, the selectively deposited barrier layer may be removed to form air gaps between the patterned metal layer and the dielectric layer.

公开(公告)号：US11227833B2

公开(公告)日：2022-01-18

申请号：US16571825

申请日：2019-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING, CO., LTD.

Inventor： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC: H01L23/52 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522

Abstract: A method for forming an interconnect structure is provided. The method for forming the interconnect structure includes forming a first dielectric layer over a substrate, forming a first conductive feature through the first dielectric layer, forming a first blocking layer on the first conductive feature, forming a first etching stop layer over the first dielectric layer and exposing the first blocking layer, removing at least a portion of the first blocking layer, forming a first metal bulk layer over the first etching stop layer and the first conductive feature, and etching the first metal bulk layer to form a second conductive feature electrically connected to the first conductive feature.