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公开(公告)号:USD860178S1
公开(公告)日:2019-09-17
申请号:US29659838
申请日:2018-08-13
Applicant: Samsung Electronics Co., Ltd.
Designer: Sanghoon Song , Youn-Gun Jung , Yoonyoung Choi , Junyoung Lee
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公开(公告)号:USD816055S1
公开(公告)日:2018-04-24
申请号:US29598693
申请日:2017-03-28
Applicant: Samsung Electronics Co., Ltd.
Designer: Sanghoon Song , Youn-Gun Jung , Yoonyoung Choi , Junyoung Lee
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公开(公告)号:US12048143B2
公开(公告)日:2024-07-23
申请号:US17392775
申请日:2021-08-03
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jiyoung Ahn , Yongseok Ahn , Hyunyong Kim , Minsub Um , Ju Hyung We , Joonkyu Rhee , Yoonyoung Choi
IPC: H10B12/00
CPC classification number: H10B12/315 , H10B12/0335 , H10B12/053 , H10B12/34 , H10B12/482 , H10B12/485
Abstract: A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer.
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公开(公告)号:US11637174B2
公开(公告)日:2023-04-25
申请号:US17036731
申请日:2020-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yoonyoung Choi , SangJae Park , Dongkyun Lee
IPC: H01L49/02 , H01L27/108
Abstract: An integrated circuit device including a lower electrode on a substrate, the lower electrode including a first lower electrode portion extending in a first direction perpendicular to a top surface of the substrate and including a first main region and a first top region, and a second lower electrode portion extending in the first direction on the first lower electrode portion and including a second main region and a second top region; a first top supporting pattern surrounding at least a portion of a side wall of the first top region of the first lower electrode portion; and a second top supporting pattern surrounding at least a portion of a side wall of the second top region of the second lower electrode portion, and the second lower electrode portion includes a protrusion protruding outward to the second top supporting pattern.
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公开(公告)号:US11302698B2
公开(公告)日:2022-04-12
申请号:US16829025
申请日:2020-03-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yoonyoung Choi , Sungsoo Yim , Byeongmoo Kang , Seongmo Koo , Sejin Park , Jinwoo Bae
IPC: H01L27/108 , H01L49/02
Abstract: A semiconductor device includes a transistor on a semiconductor substrate including a first area and a second area, and having a gate structure and an impurity area, a first interlayer insulating film covering the transistor, and having a contact plug electrically connected to the impurity area, a capacitor including a lower electrode on the first interlayer insulating film in the second area and electrically connected to the contact plug, a dielectric film coating a surface of the lower electrode, and an upper electrode on the dielectric film, and a support layer in contact with an upper side surface of the lower electrode to support the lower electrode, and extending to the first area, in which the support layer has a step between the first area and the second area.
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公开(公告)号:US20210391259A1
公开(公告)日:2021-12-16
申请号:US17129083
申请日:2020-12-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jiyoung Ahn , Seunguk Han , Sunghwan Kim , Seoryong Park , Kiseok Lee , Yoonyoung Choi , Taehee Han , Jiseok Hong
IPC: H01L23/528
Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.
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37.
公开(公告)号:US11152368B2
公开(公告)日:2021-10-19
申请号:US16908833
申请日:2020-06-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Yoonyoung Choi , Byunghyun Lee , Seungjin Kim , Byeongjoo Ku , Sangjae Park , Hangeol Lee
IPC: H01L27/108 , H01L21/768 , H01L23/532
Abstract: A semiconductor device includes a substrate, a storage node electrode disposed on the substrate, a dielectric layer at least partially covering the storage node electrode, and a plate electrode dispose on the dielectric layer. The storage node electrode has a pillar shape, and includes a seam disposed therein. The storage node electrode includes a concave side surface disposed at a higher level than the seam.
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公开(公告)号:USD918886S1
公开(公告)日:2021-05-11
申请号:US29712052
申请日:2019-11-05
Applicant: Samsung Electronics Co., Ltd.
Designer: Sanghoon Song , Youn-Gun Jung , Yoonyoung Choi , Junyoung Lee
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公开(公告)号:USD874420S1
公开(公告)日:2020-02-04
申请号:US29630778
申请日:2017-12-22
Applicant: Samsung Electronics Co., Ltd.
Designer: Youngjun Cho , Sanghoon Song , Junyoung Lee , Munhee Jang , Youn-Gun Jung , Yoonyoung Choi
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公开(公告)号:USD860151S1
公开(公告)日:2019-09-17
申请号:US29623857
申请日:2017-10-27
Applicant: Samsung Electronics Co., Ltd.
Designer: Youngjun Cho , Sanghoon Song , Junyoung Lee , Munhee Jang , Youn-Gun Jung , Yoonyoung Choi
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