公开(公告)号：US20210391259A1

公开(公告)日：2021-12-16

申请号：US17129083

申请日：2020-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoung Ahn ,  Seunguk Han ,  Sunghwan Kim ,  Seoryong Park ,  Kiseok Lee ,  Yoonyoung Choi ,  Taehee Han ,  Jiseok Hong

IPC: H01L23/528

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

公开(公告)号：US20230351189A1

公开(公告)日：2023-11-02

申请号：US18171433

申请日：2023-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehee Han ,  Juyeon Kang ,  Changho Ryu

IPC: G06N3/084 ,  G06N3/0464

CPC classification number: G06N3/084 ,  G06N3/0464

Abstract: In a method of training a binarized neural network (BNN), a binarized weight set is generated by applying a clipping function to a weight set. Output data is generated by sequentially performing a forward computation on the binarized neural network based on input data and the binarized weight set. A gradient of the weight set is generated by sequentially performing a backward computation on the binarized neural network based on loss calculated from the output data. The binarized neural network is trained by updating the weight set based on the gradient of the weight set and changing a range of the clipping function.

公开(公告)号：US20200219833A1

公开(公告)日：2020-07-09

申请号：US16704217

申请日：2019-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngkwan LEE ,  Youngsik HUR ,  Junghyun Cho ,  Taehee Han ,  Jongrok Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package may include: a connection structure including an insulating member having a first surface having a recess portion and a second surface opposing the first surface, a plurality of first pads disposed on a bottom surface of the recess portion, a plurality of second pads embedded in the second surface of the insulating member, and a redistribution layer disposed between the plurality of first pads and the plurality of second pads and connected to the plurality of first and second pads; a semiconductor chip disposed on the first surface of the insulating member and having a plurality of connection electrodes electrically connected, respectively, to the plurality of first pads; and a passivation layer disposed on the second surface of the insulating member and having a plurality of openings exposing, respectively, the plurality of second pads.

公开(公告)号：US11239148B2

公开(公告)日：2022-02-01

申请号：US16684808

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngkwan Lee ,  Youngsik Hur ,  Taehee Han

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552

Abstract: A semiconductor package includes a core layer formed of a ferromagnetic material, and includes a frame passing through the core layer and having a through-hole, a semiconductor chip disposed in the through-hole of the frame, and having an active surface on which a connection pad is disposed, and an inactive surface opposite to the active surface, an encapsulant covering at least a portion of the semiconductor chip, and a first connection structure including a first redistribution layer disposed on the active surface of the semiconductor chip and electrically connected to the connection pad.

公开(公告)号：US20200168518A1

公开(公告)日：2020-05-28

申请号：US16681341

申请日：2019-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngkwan LEE ,  Youngsik Hur ,  Taehee Han ,  Yonghoon Kim ,  Yuntae Lee

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame; a first connection structure on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a first semiconductor chip on the first connection structure within the cavity; an encapsulant encapsulating the first semiconductor chip and covering the second surface of the frame; a second connection structure including a second redistribution layer including a first redistribution pattern and first connection vias; and a second semiconductor chip disposed on the second connection structure and having connection pads connected to the second redistribution layer.

公开(公告)号：US11908797B2

公开(公告)日：2024-02-20

申请号：US17129083

申请日：2020-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoung Ahn ,  Seunguk Han ,  Sunghwan Kim ,  Seoryong Park ,  Kiseok Lee ,  Yoonyoung Choi ,  Taehee Han ,  Jiseok Hong

IPC: H01L23/528 ,  H01L29/06 ,  H10B12/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/764

CPC classification number: H01L23/5283 ,  H01L21/764 ,  H01L21/7682 ,  H01L29/0649 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488 ,  H01L23/5222 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/34

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

公开(公告)号：US11469148B2

公开(公告)日：2022-10-11

申请号：US16681341

申请日：2019-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngkwan Lee ,  Youngsik Hur ,  Taehee Han ,  Yonghoon Kim ,  Yuntae Lee

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes: a frame having a cavity and including a wiring structure connecting first and second surfaces of the frame; a first connection structure on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a first semiconductor chip on the first connection structure within the cavity; an encapsulant encapsulating the first semiconductor chip and covering the second surface of the frame; a second connection structure including a second redistribution layer including a first redistribution pattern and first connection vias; and a second semiconductor chip disposed on the second connection structure and having connection pads connected to the second redistribution layer.