Semiconductor devices with alignment keys

    公开(公告)号:US10026694B2

    公开(公告)日:2018-07-17

    申请号:US15608747

    申请日:2017-05-30

    Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

    Method and system for providing Wi-Fi service by Wi-Fi device

    公开(公告)号:US09736691B2

    公开(公告)日:2017-08-15

    申请号:US14529957

    申请日:2014-10-31

    CPC classification number: H04W12/06 H04L63/0853 H04L67/16 H04W8/005

    Abstract: A method and a system for providing a Wireless Fidelity (Wi-Fi) service, in which when multiple counterpart devices are selected based on manufacturer information and support information on supported functions and capability defined in a service information field of each beacon message or each probe response message, a final device is determined by checking multiple pieces of signal information of the selected counterpart devices, are provided. The method includes receiving messages from multiple counterpart devices, selecting one or more counterpart devices, each of which supports a requested service, from an identical manufacturer when the messages are received, checking multiple pieces of signal information of the selected counterpart devices when the number of the selected counterpart devices is greater than one, and determining a device having the signal information satisfying set conditions as a final device.

    Semiconductor memory device and method of fabricating the same

    公开(公告)号:US10665592B2

    公开(公告)日:2020-05-26

    申请号:US16108786

    申请日:2018-08-22

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

    公开(公告)号:US20190164975A1

    公开(公告)日:2019-05-30

    申请号:US16108786

    申请日:2018-08-22

    Abstract: Provided are a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include: a first impurity doped region and a second impurity doped region spaced apart from each other in a semiconductor substrate, a bit line electrically connected to the first impurity doped region and crossing over the semiconductor substrate, a storage node contact electrically connected to the second impurity doped region, a first spacer and a second spacer disposed between the bit line and the storage node contact, and an air gap region disposed between the first spacer and the second spacer. The first spacer may cover a sidewall of the bit line, and the second spacer may be adjacent to the storage node contact. A top end of the first spacer may have a height higher than a height of a top end of the second spacer.

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