公开(公告)号：US20210265755A1

公开(公告)日：2021-08-26

申请号：US17316596

申请日：2021-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sompong Paul Olarig ,  Fred Worley

IPC: H01R12/73 ,  H01R12/72 ,  H01R43/20 ,  H01R43/26 ,  H05K1/18 ,  H05K3/30

Abstract: In an example, a device includes: a printed circuit board (PCB); at least one solid state drive (SSD) connected at a first side of the PCB via at least one SSD connector; at least one field programmable gate array (FPGA) mounted on the PCB at a second side of the PCB; and at least one connector attached to the PCB at a third side of the PCB, wherein the device is configured to operate in a first speed from a plurality of operating speeds based on a first input received via the at least one connector.

公开(公告)号：US20210263871A1

公开(公告)日：2021-08-26

申请号：US17316385

申请日：2021-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Fred Worley ,  Harry Rogers ,  Sreenivas Krishnan ,  Zhan Ping ,  Michael Scriber

IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40

Abstract: A flexible storage system. A storage motherboard accommodates, on a suitable connector, a storage adapter circuit that provides protocol translation between a host bus interface and a storage interface, and that provides routing, to accommodate a plurality of mass storage devices that may be connected to the storage adapter circuit through the storage motherboard. The storage adapter circuit may be replaced with a circuit supporting a different host interface or a different storage interface.

公开(公告)号：US11100024B2

公开(公告)日：2021-08-24

申请号：US16950624

申请日：2020-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Fred Worley ,  Son Pham

IPC: G06F3/00 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

Abstract: A system includes a fabric switch including a motherboard, a baseboard management controller (BMC), a network switch configured to transport network signals, and a PCIe switch configured to transport PCIe signals; a midplane; and a plurality of device ports. Each of the plurality of device ports is configured to connect a storage device to the motherboard of the fabric switch over the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable in multiple modes based a protocol established over a fabric connection between the system and the storage device.

公开(公告)号：US20210019272A1

公开(公告)日：2021-01-21

申请号：US17063501

申请日：2020-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Fred Worley ,  Son Pham

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

Abstract: A system includes a fabric switch including a motherboard, a baseboard management controller (BMC), a network switch configured to transport network signals, and a PCIe switch configured to transport PCIe signals; a midplane; and a plurality of device ports. Each of the plurality of device ports is configured to connect a storage device to the motherboard of the fabric switch over the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable in multiple modes based a protocol established over a fabric connection between the system and the storage device.

公开(公告)号：US10719474B2

公开(公告)日：2020-07-21

申请号：US15921400

申请日：2018-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas Kachare ,  Fred Worley ,  Xuebin Yao

IPC: G06F3/06 ,  G06F13/42 ,  H04L12/931 ,  G06F9/4401 ,  G06F13/16 ,  G06F13/40 ,  G06N20/00

Abstract: A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

公开(公告)号：US20200183583A1

公开(公告)日：2020-06-11

申请号：US16270434

申请日：2019-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas P. Kachare ,  Vijay Balakrishnan ,  Stephen G. Fischer ,  Fred Worley ,  Anahita Shayesteh ,  Zvi Guz

IPC: G06F3/06 ,  G06F9/54 ,  G06F9/38

Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n−1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.

公开(公告)号：US10585843B2

公开(公告)日：2020-03-10

申请号：US16124179

申请日：2018-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas P. Kachare ,  Fred Worley ,  Harry Rogers ,  Wentao Wu ,  Nagarajan Subramaniyan

IPC: G06F13/16 ,  G06F13/42 ,  G06F9/445 ,  G06F13/40

Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a physical function (PF) to expose the storage device, a second function to expose the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. A downstream filter associated with the downstream port may intercept an acceleration instruction associated with a downstream Filter Address Range (FAR) received from the storage device and deliver the acceleration instruction to the APM-F, the acceleration instruction being. An upstream filter associated with the upstream port may intercept an acceleration instruction received from the processor and deliver the second acceleration instruction to the APM-F. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

公开(公告)号：US10585749B2

公开(公告)日：2020-03-10

申请号：US15789884

申请日：2017-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ramdas P. Kachare ,  Fred Worley ,  Stephen Fischer ,  Oscar Pinto

IPC: G06F11/10 ,  H03M13/15

Abstract: A system and method for distributed erasure coding. A plurality of storage devices is directly connected to one or more host computers, without an intervening central controller distributing data to the storage devices and providing data protection. Parity codes are stored in one or more dedicated storage devices or distributed over a plurality of the storage devices. When a storage device receives a write command, it calculates a partial parity code, and, if the parity code for the data being written is on another storage device, sends the partial parity code to the other storage device, which updates the parity code using the partial parity code.

公开(公告)号：US20190280411A1

公开(公告)日：2019-09-12

申请号：US16033141

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Fred Worley

IPC: H01R12/73 ,  H01R12/72 ,  H01R43/20 ,  H01R43/26 ,  H05K1/18 ,  H05K3/30

Abstract: In an example, a device includes: a printed circuit board (PCB); at least one solid state drive (SSD) connected at a first side of the PCB via at least one SSD connector; at least one field programmable gate array (FPGA) mounted on the PCB at a second side of the PCB; and at least one connector attached to the PCB at a third side of the PCB, wherein the device is configured to operate in a first speed from a plurality of operating speeds based on a first input received via the at least one connector.

公开(公告)号：US20190278720A1

公开(公告)日：2019-09-12

申请号：US16115338

申请日：2018-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sompong Paul Olarig ,  Fred Worley

IPC: G06F13/16 ,  G06F3/06

Abstract: According to some example embodiments according to the present disclosure, a device includes a printed circuit board (PCB); a solid state drive (SSD) connected at a first side of the PCB via at least one SSD connector; at least one field programmable gate array (FPGA) attached to the PCB at a second side of the PCB; and at least one front end connector attached to the PCB at a third side of the PCB, wherein the device is configured to process data stored in the SSD based on a command received via the at least one front end connector.