Devices capable of detecting and allocating power and associated method

    公开(公告)号:US11733764B2

    公开(公告)日:2023-08-22

    申请号:US17023360

    申请日:2020-09-16

    CPC classification number: G06F1/3287 H02J1/14

    Abstract: A device capable of self-detecting and self-allocating additional power and associated method are disclosed. The device includes a first module to route current from first power pins to a voltage rail having the first voltage level. The device includes a second module coupled to second power pins associated with a second voltage level. The second module routes current from the second power pins to the voltage rail having the first voltage level via a connecting voltage rail. The method includes determining, by the device, whether or not a presence of unused power pins is detected. Based on the detection, the method includes calculating a total amount of available additional power, repurposing the unused power pins as actively used power pins, and updating a power budget value based on the total amount of available additional power. The device may dynamically allocate power to accelerators based on a power allocation table and the power budget value.

    SSD architecture for FPGA based acceleration

    公开(公告)号:US10592463B2

    公开(公告)日:2020-03-17

    申请号:US16124182

    申请日:2018-09-06

    Abstract: A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream endpoint enables communication with the processor; two downstream root ports enable communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include two endpoints of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.

    SYSTEM AND METHOD FOR DISTRIBUTED ERASURE CODING

    公开(公告)号:US20190050289A1

    公开(公告)日:2019-02-14

    申请号:US15789884

    申请日:2017-10-20

    Abstract: A system and method for distributed erasure coding. A plurality of storage devices is directly connected to one or more host computers, without an intervening central controller distributing data to the storage devices and providing data protection. Parity codes are stored in one or more dedicated storage devices or distributed over a plurality of the storage devices. When a storage device receives a write command, it calculates a partial parity code, and, if the parity code for the data being written is on another storage device, sends the partial parity code to the other storage device, which updates the parity code using the partial parity code.

    System and method for distributed erasure coding

    公开(公告)号:US10585749B2

    公开(公告)日:2020-03-10

    申请号:US15789884

    申请日:2017-10-20

    Abstract: A system and method for distributed erasure coding. A plurality of storage devices is directly connected to one or more host computers, without an intervening central controller distributing data to the storage devices and providing data protection. Parity codes are stored in one or more dedicated storage devices or distributed over a plurality of the storage devices. When a storage device receives a write command, it calculates a partial parity code, and, if the parity code for the data being written is on another storage device, sends the partial parity code to the other storage device, which updates the parity code using the partial parity code.

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