公开(公告)号：US20160156214A1

公开(公告)日：2016-06-02

申请号：US14941213

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Geun YOON ,  Chul-Woo PARK ,  Kisun LEE ,  Ku-Chul JUNG

IPC: H02J7/00

CPC classification number: H02J7/0086 ,  H02J7/0029 ,  H02J7/0031 ,  H02J7/0063 ,  H02J7/0068 ,  H02J2007/0037 ,  H02J2007/0039 ,  H02J2007/004

Abstract: A charging control method and an electronic device for handling the method are provided. A power management device includes a power switch for providing a power path between a battery and a terminal set, and a control module configured to control the power switch to provide a charging function by forming the power path between the battery and the terminal set and provide a battery protection function by forming a discharging path or a charging path with respect to the battery.

Abstract translation: 提供了一种用于处理该方法的充电控制方法和电子设备。 电源管理装置包括用于提供电池和终端机之间的电源路径的电源开关，以及配置为通过在电池和终端机之间形成电源路径来控制电源开关以提供充电功能的控制模块，并提供 通过形成相对于电池的放电路径或充电路径的电池保护功能。

公开(公告)号：US20160155515A1

公开(公告)日：2016-06-02

申请号：US14817212

申请日：2015-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Chul-Woo PARK ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA ,  Seong-Jin JANG

IPC: G11C29/44 ,  G11C29/38 ,  G11C29/42 ,  G11C11/4096

CPC classification number: G11C29/4401 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4096 ,  G11C29/42 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.

Abstract translation: 半导体存储器件包括存储单元阵列和测试电路。 测试电路从存储单元阵列读取数据流，配置为在比较数据流中的每个第一单元的比特时，将第一单元中的相应比特作为每个第二单元进行比较，并输出包括通过/失败信息的故障信息信号 数据流和关于数据流的附加信息，在半导体存储器件的测试模式中。

公开(公告)号：US20150243345A1

公开(公告)日：2015-08-27

申请号：US14517255

申请日：2014-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua KIM ,  Chul-Woo PARK

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/4082 ,  G11C5/04 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622

Abstract: A memory module may include m memory devices. Each of the m memory devices may be divided into n regions each region including a plurality of rows corresponding to row addresses, where m and n are integers equal to or greater than 2. An address detector included in each of the m memory devices, wherein for each of the address detectors, the address detector may be configured to count a number of accesses to a particular row address included in one region of each of the m memory devices during a predetermined time period, and be configured to output a detect signal when the number of the counted accesses reaches a reference value. Each of the max-count address generators may be configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other max-count address generators count accesses.

Abstract translation: 存储器模块可以包括m个存储器件。 每个m个存储器件可以被划分为n个区域，每个区域包括对应于行地址的多个行，其中m和n是等于或大于2的整数。一种地址检测器，包括在每个m个存储器件中，其中 对于每个地址检测器，地址检测器可以被配置为在预定时间段内对包括在每个m个存储器件的一个区域中的特定行地址的访问次数进行计数，并且被配置为当 计数访问次数达到参考值。 每个最大计数地址生成器可以被配置为对与其他最大计数地址生成器计数访问的行地址集合不同的一组行地址来计数访问次数。

公开(公告)号：US20150243338A1

公开(公告)日：2015-08-27

申请号：US14514416

申请日：2014-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Chul-Woo PARK ,  Si-Hong KIM ,  KWANG-IL PARK ,  Jae-Youn YOUN

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C11/4087

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Abstract translation: 存储器件包括存储单元阵列，集中访问的行检测电路和刷新控制电路。 存储单元阵列包括多个存储单元行。 集中访问的行检测电路基于多个存储单元行中的每一个的累积访问时间，生成指示多个存储单元行中的集中访问的存储单元行的集中访问的行地址。 当从集中访问的行检测单元接收到集中访问的行地址时，刷新控制单元优先刷新与由强行访问的行地址指示的集中访问的存储单元行相邻的相邻存储单元行。 存储器件有效地降低了数据丢失率。

公开(公告)号：US20150067448A1

公开(公告)日：2015-03-05

申请号：US14305095

申请日：2014-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Pil SON ,  Young-Soo SOHN ,  Uk-Song KANG ,  Chul-Woo PARK ,  Jung-Hwan CHOI ,  Won-Il BAE ,  Kyo-Min SOHN

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411

Abstract: In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

Abstract translation: 在操作存储器件的方法中，接收来自存储器控制器的命令和第一地址。 从存储器件的存储单元阵列读取包括对应于第一地址的第一组数据，对应于第二地址的第二组数据和读取奇偶校验数据的读码字。 通过使用基于读取的线字的ECC电路的操作错误检查和校正（ECC）来生成校正的数据。

公开(公告)号：US20140237177A1

公开(公告)日：2014-08-21

申请号：US14171343

申请日：2014-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Soo YU ,  Chul-Woo PARK ,  Jung-Bae LEE

IPC: G11C11/406

CPC classification number: G11C11/40607 ,  G11C5/04 ,  G11C11/40611

Abstract: A memory module includes a master memory device and at least one slave memory device. The master memory device may generate a refresh clock signal, and perform a refresh operation in synchronization with the refresh clock signal. The slave memory device may be connected to receive the refresh clock signal, and perform a refresh operation in synchronization with the refresh clock signal.

Abstract translation: 存储器模块包括主存储器设备和至少一个从存储器设备。 主存储器件可以产生刷新时钟信号，并且与刷新时钟信号同步地执行刷新操作。 从存储器件可以被连接以接收刷新时钟信号，并且与刷新时钟信号同步地执行刷新操作。