公开(公告)号：US20230378083A1

公开(公告)日：2023-11-23

申请号：US18172534

申请日：2023-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum LEE ,  Jimo GU ,  Jiyoung KIM ,  Sukkang SUNG

IPC: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/544 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H01L2223/54426

Abstract: A semiconductor device may include an align key on a plate layer. The align key may include a first align layer connected to a second align layer. The first align layer may have a first length in a first direction, a second length in a second direction, and an air gap in the first align layer. The second align layer may be on the first align layer and may have a third length. The first direction may be perpendicular to an upper surface of the plate layer. The second length may be smaller than the first length. The third length may be smaller than the second length in the second direction.

公开(公告)号：US20230012115A1

公开(公告)日：2023-01-12

申请号：US17570874

申请日：2022-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho KIM ,  Jiwon KIM ,  Joonsung KIM ,  Sukkang SUNG ,  Sangdon LEE ,  Jong-Min LEE ,  Euntaek JUNG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional semiconductor devices including a substrate, a stack structure including gate electrodes on the substrate and string selection electrodes spaced apart from each other on the gate electrodes, a first separation structure running in a first direction across the stack structure and being between the string selection electrodes, vertical channel structures penetrating the stack structure, and bit lines connected to the vertical channel structures and extending in a second direction may be provided. A first subset of the vertical channel structures is connected in common to one of the bit lines. The vertical channel structures of the first subset may be adjacent to each other in the second direction across the first separation structure. Each of the string selection electrodes may surround each of the vertical channel structures of the first subset.

公开(公告)号：US20220122933A1

公开(公告)日：2022-04-21

申请号：US17460873

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin HWANG ,  Jiwon KIM ,  Jaeho AHN ,  Joonsung LIM ,  Sukkang SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A memory device including a first structure; and a second structure on the first structure, wherein the first structure includes a first substrate; a peripheral circuit on the first substrate; a first insulating layer covering the first substrate and the peripheral circuit; and a first bonding pad on the first insulating layer, the second structure includes a second substrate; a memory cell array on a first surface of the second substrate; a second insulating layer covering the first surface of the second substrate and the memory cell array; a conductive pattern at least partially recessed from a second surface of the second substrate; and a second bonding pad on the second insulating layer, the first bonding pad is in contact with the second bonding pad, and the conductive pattern is spaced apart from the second insulating layer.