公开(公告)号：US20150084041A1

公开(公告)日：2015-03-26

申请号：US14464785

申请日：2014-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Gi Hur ,  Sangsu Kim ,  Junggil Yang ,  Changjae Yang ,  Dongkyu Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/12

CPC classification number: H01L29/7832 ,  H01L27/1104 ,  H01L29/12 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/7831

Abstract: A gate-all-around (GAA) semiconductor device can include a fin structure that includes alternatingly layered first and second semiconductor patterns. A source region can extend into the alternatingly layered first and second semiconductor patterns and a drain region can extend into the alternatingly layered first and second semiconductor patterns. A gate electrode can extend between the source region and the drain region and surround channel portions of the second semiconductor patterns between the source region and the drain region to define gaps between the source and drain regions. A semiconductor oxide can be on first side walls of the gap that face the source and drain regions and can be absent from at least one of second side walls of the gaps that face the second semiconductor patterns. A gate insulating layer can be on the first side walls of the gaps between the gate electrode and the semiconductor oxide.

Abstract translation: 栅极全能（GAA）半导体器件可以包括鳍结构，其包括交替分层的第一和第二半导体图案。 源极区域可以延伸到交替层叠的第一和第二半导体图案中，并且漏极区域可以延伸到交替层叠的第一和第二半导体图案中。 栅电极可以在源极区域和漏极区域之间延伸并且围绕源极区域和漏极区域之间的第二半导体图案的通道部分，以限定源极和漏极区域之间的间隙。 半导体氧化物可以位于与源极和漏极区域相对的间隙的第一侧壁上，并且可以不存在面对第二半导体图案的间隙的第二侧壁中的至少一个。 栅极绝缘层可以位于栅电极和半导体氧化物之间的间隙的第一侧壁上。