公开(公告)号：US11094103B2

公开(公告)日：2021-08-17

申请号：US16364829

申请日：2019-03-26

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Chun Yu ,  Chihong Zhang ,  Hongjiang Shang ,  Zilin Ying ,  Fei Wei

IPC: G06T15/04 ,  G06F9/54 ,  G06F9/38

Abstract: Example techniques are described for generating graphics content by obtaining texture operation instructions corresponding to a texture operation, in response to determining at least one of insufficient general purpose register space is available for the texture operation or insufficient wave slots are available for the texture operation, generating an indication that the texture operation corresponds to a deferred wave, executing the texture operation, sending, to a texture processor, initial texture sample instructions corresponding to the texture operation that was executed, and receiving texture mapped data corresponding to the initial texture sample instructions.

公开(公告)号：US10592468B2

公开(公告)日：2020-03-17

申请号：US15209057

申请日：2016-07-13

Applicant: QUALCOMM Incorporated

Inventor： Liang Han ,  Xiangdong Jin ,  Lin Chen ,  Yun Du ,  Alexei Vladimirovich Bourd

IPC: G06F15/80 ,  G06F9/30 ,  G06F13/40 ,  G06F9/38

Abstract: Techniques are described to perform a shuffle operation. Rather than using an all-lane to all-lane cross bar, a shuffler circuit having a smaller cross bar is described. The shuffler circuit performs the shuffle operation piecewise by reordering data received from processing lanes and outputting the reordered data.

公开(公告)号：US10133572B2

公开(公告)日：2018-11-20

申请号：US14268215

申请日：2014-05-02

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Lin Chen ,  Yun Du ,  Alexei Vladimirovich Bourd

IPC: G06F9/30 ,  G06F9/38

Abstract: A SIMD processor may be configured to determine one or more active threads from a plurality of threads, select one active thread from the one or more active threads, and perform a divergent operation on the selected active thread. The divergent operation may be a serial operation.

公开(公告)号：US20180018299A1

公开(公告)日：2018-01-18

申请号：US15209057

申请日：2016-07-13

Applicant: QUALCOMM Incorporated

Inventor： Liang Han ,  Xiangdong Jin ,  Lin Chen ,  Yun Du ,  Alexei Vladimirovich Bourd

IPC: G06F15/80 ,  G06F9/38

CPC classification number: G06F15/8007 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3887 ,  G06F13/4013 ,  G06F15/80 ,  G06F15/8053

Abstract: Techniques are described to perform a shuffle operation. Rather than using an all-lane to all-lane cross bar, a shuffler circuit having a smaller cross bar is described. The shuffler circuit performs the shuffle operation piecewise by reordering data received from processing lanes and outputting the reordered data.

公开(公告)号：US09665370B2

公开(公告)日：2017-05-30

申请号：US14462932

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Lin Chen ,  Andrew Evan Gruber ,  Chihong Zhang ,  Chun Yu

IPC: G06T15/00 ,  G06F9/30 ,  G06T1/20 ,  G06F9/38 ,  G06F9/45

CPC classification number: G06F9/30098 ,  G06F8/441 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/3828 ,  G06F9/3859 ,  G06T1/20 ,  G06T2200/28

Abstract: Techniques are described in which an indication is included to indicate a last use of an intermediate value generated as part of determining a final value is not be stored in a general purpose register (GPR). A processing unit avoids storing the intermediate value in the GPR based on the indication because the intermediate value is no longer needed for determining the final value.