公开(公告)号：US09698727B1

公开(公告)日：2017-07-04

申请号：US14965760

申请日：2015-12-10

Applicant: QUALCOMM Incorporated

Inventor： Alireza Khalili ,  Mazhareddin Taghivand ,  Amirpouya Kavousian

IPC: H03B5/08 ,  H03B1/04 ,  H03B5/12 ,  H01F27/28

CPC classification number: H03B1/04 ,  H01F27/2804 ,  H01L23/5227 ,  H01L28/00 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B2200/004 ,  H03B2200/009 ,  H03B2202/01 ,  H03B2202/05

Abstract: A two-walled coupled inductor includes an outer wall and an inner wall separated by a slit. The outer wall has a first width and the inner wall has a second width. The inner wall and the outer wall may be configured to be coupled to oscillator circuitry. The two-walled coupled inductor may include an electrically conductive stub coupled to the outer wall to be coupled to a power supply. A common mode current flows through the outer wall, and the stub if one is present, and a differential mode current flows through both the outer wall and the inner wall, but not the stub. The first and second widths, and dimensions of the stub, may be sized to increase an inductance of the common mode compared to an inductance of the differential mode, thereby reducing phase noise of the inductor-based resonator.

公开(公告)号：US09647638B2

公开(公告)日：2017-05-09

申请号：US14331685

申请日：2014-07-15

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Bagher Vahid Far ,  Cheng-Han Wang ,  Jesse Aaron Richmond ,  Thinh Cat Nguyen ,  Abbas Komijani ,  Yashar Rajavi ,  Alireza Khalili

IPC: G06F17/10 ,  H03H11/04 ,  H03H11/12 ,  H04B1/10 ,  H04B1/525

CPC classification number: H03H11/0433 ,  H03H11/1252 ,  H04B1/109 ,  H04B1/525

Abstract: A method and apparatus for minimizing transmit signal interference is provided. The method includes the steps of: receiving a signal and amplifying the received signal. The received signal is then mixed with an intermediate frequency signal to obtain a baseband modulated signal. The baseband modulated signal is first filtered in an RC filter. The resulting signal is then divided by a preselected amount and the first divided portion is sent to a main path of a biquad filter, which produces a first stage biquad filtered signal. The second portion of the divided signal is sent to an auxiliary path of the biquad filter, and produces a second filtered signal. The first and second signals are then recombined and sent to the second stage of the biquad filter, where further filtering takes place.

公开(公告)号：US09553545B1

公开(公告)日：2017-01-24

申请号：US14983180

申请日：2015-12-29

Applicant: QUALCOMM Incorporated

Inventor： Alireza Khalili ,  Afshin Babveyh ,  Mazhareddin Taghivand

IPC: H03B5/36

CPC classification number: H03B5/364

Abstract: Differential crystal oscillator circuits are disclosed that may provide low-power, low phase noise operation, and prevent latching at low frequency by providing a low impedance DC path using active super diodes.

Abstract translation: 公开了差分晶体振荡器电路，其可以提供低功率，低相位噪声操作，并且通过使用有源超级二极管提供低阻抗DC路径来防止在低频下的锁存。

公开(公告)号：US20160028349A1

公开(公告)日：2016-01-28

申请号：US14338241

申请日：2014-07-22

Applicant: QUALCOMM Incorporated

Inventor： Yashar Rajavi ,  Amirpouya Kavousian ,  Alireza Khalili ,  Mohammad Bagher Vahid Far ,  Abbas Komijani

IPC: H03B5/36

CPC classification number: H03B5/364 ,  H03B5/06 ,  H03B5/36 ,  H03B2200/004 ,  H03B2200/0094

Abstract: A differential crystal oscillator circuit, including: first and second output terminals; a cross-coupled oscillation unit including first and second transistors cross-coupled to the first and second output terminals; first and second metal-oxide semiconductor field-effect transistor (MOSFET) diodes, each MOSFET diode including a resistor connected between gate and drain terminals, wherein the first MOSFET diode couples to the first transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the first transistor, wherein the second MOSFET diode couples to the second transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the second transistor; and a reference resonator coupled between the first and second output terminals to establish an oscillation frequency.

Abstract translation: 一种差分晶体振荡器电路，包括：第一和第二输出端子; 交叉耦合振荡单元，包括交叉耦合到第一和第二输出端的第一和第二晶体管; 第一和第二金属氧化物半导体场效应晶体管（MOSFET）二极管，每个MOSFET二极管包括连接在栅极和漏极端子之间的电阻器，其中第一MOSFET二极管耦合到第一晶体管以在低频和高电平下提供低阻抗负载 在第一晶体管的较高频率处的阻抗负载，其中所述第二MOSFET二极管耦合到所述第二晶体管，以在低频处提供低阻抗负载，并以较高频率向所述第二晶体管提供高阻抗负载; 以及耦合在第一和第二输出端子之间以建立振荡频率的参考谐振器。

公开(公告)号：US09246435B1

公开(公告)日：2016-01-26

申请号：US14617716

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Amirpouya Kavousian ,  Yashar Rajavi ,  Alireza Khalili ,  Mohammad Bagher Vahid Far ,  Abbas Komijani

IPC: H03B5/06 ,  H03B5/36 ,  H03K3/03

CPC classification number: H03B5/06 ,  H03B5/362 ,  H03B5/364 ,  H03B5/366 ,  H03B2200/0094 ,  H03K3/014 ,  H03K3/0307 ,  H03K3/0315 ,  H03L3/00 ,  H03L7/00

Abstract: A method and apparatus for charging a crystal oscillator are provided. A voltage generating module outputs a ramp voltage signal to a ring oscillator. The ring oscillator generates and outputs a waveform based on the ramp voltage signal. The ramp voltage signal facilitates the ring oscillator to output the waveform at a frequency that varies with time, wherein the varying frequency is within a frequency range of the crystal oscillator. An inverter generates a digital input signal based on the waveform. The digital input signal is sent to an input of the crystal oscillator for charging the crystal oscillator. A feedback module outputs a feedback signal based on the digital input signal, wherein the feedback signal controls the voltage generating module to generate a fixed voltage signal that facilitates the ring oscillator to output the waveform at a frequency that is equal to a resonance frequency of the crystal oscillator.

Abstract translation: 提供了一种用于对晶体振荡器充电的方法和装置。 电压产生模块向环形振荡器输出斜坡电压信号。 环形振荡器产生并输出基于斜坡电压信号的波形。 斜坡电压信号有助于环形振荡器以随时间变化的频率输出波形，其中变化的频率在晶体振荡器的频率范围内。 逆变器根据波形产生数字输入信号。 数字输入信号被发送到晶体振荡器的输入端，用于对晶体振荡器充电。 反馈模块基于数字输入信号输出反馈信号，其中反馈信号控制电压产生模块以产生固定电压信号，其有助于环形振荡器以等于的频率的频率输出波形 晶体振荡器。

公开(公告)号：US20160020752A1

公开(公告)日：2016-01-21

申请号：US14331685

申请日：2014-07-15

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Bagher Vahid Far ,  Cheng-Han Wang ,  Jesse Aaron Richmond ,  Thinh Cat Nguyen ,  Abbas Komijani ,  Yashar Rajavi ,  Alireza Khalili

IPC: H03H17/02

CPC classification number: H03H11/0433 ,  H03H11/1252 ,  H04B1/109 ,  H04B1/525

Abstract: A method and apparatus for minimizing transmit signal interference is provided. The method includes the steps of: receiving a signal and amplifying the received signal. The received signal is then mixed with an intermediate frequency signal to obtain a baseband modulated signal. The baseband modulated signal is first filtered in an RC filter. The resulting signal is then divided by a preselected amount and the first divided portion is sent to a main path of a biquad filter, which produces a first stage biquad filtered signal. The second portion of the divided signal is sent to an auxiliary path of the biquad filter, and produces a second filtered signal. The first and second signals are then recombined and sent to the second stage of the biquad filter, where further filtering takes place.

Abstract translation: 提供一种用于最小化发射信号干扰的方法和装置。 该方法包括以下步骤：接收信号并放大所接收的信号。 然后将接收到的信号与中频信号混合以获得基带调制信号。 首先在RC滤波器中过滤基带调制信号。 然后将所得信号除以预选量，并将第一分割部分发送到双二阶滤波器的主路径，其产生第一级双二进制滤波信号。 分频信号的第二部分被发送到二叉滤波器的辅助路径，并且产生第二滤波信号。 然后将第一和第二信号重新组合并发送到二级滤波器的第二级，其中进行进一步的滤波。

公开(公告)号：US08729931B1

公开(公告)日：2014-05-20

申请号：US13757653

申请日：2013-02-01

Applicant: QUALCOMM Incorporated

Inventor： Alireza Khalili

IPC: H03K21/00

CPC classification number: H03K3/35625 ,  H03K3/0315 ,  H03K3/354

Abstract: A divide-by-two divider circuit receives a differential input signal and outputs four rail-to-rail, twenty-five percent duty cycle signals, where the frequency of the output signals is half of the frequency of the input signal. Each latch can output its output signals into loads of at least 15 fF at a frequency of at least 3 GHz so that each output signal has a phase noise of better than 160 dBc/Hz, while the latch consumes less than 0.7 mW over PVT from a supply voltage less than 1.0 volt. Each latch has a cross-coupled pair of P-channel transistors and two output signal generating branches. A static current blocking circuit in each branch prevents current flow in the branch during times when the branch is not switching its output signal. The input node of the latch is capacitively coupled to a signal source, and the DC voltage on the node is set by a bias circuit.

Abstract translation: 一个二分频分频器电路接收差分输入信号，并输出四个轨到轨二十五％的占空比信号，其中输出信号的频率是输入信号频率的一半。 每个锁存器可以以至少3 GHz的频率将其输出信号输出至少15 fF的负载，以使每个输出信号具有优于160 dBc / Hz的相位噪声，而锁存器消耗的PVT小于0.7 mW 电源电压小于1.0伏。 每个锁存器具有交叉耦合的一对P沟道晶体管和两个输出信号产生分支。 每个分支中的静态电流阻断电路在分支未切换其输出信号的时间期间防止分支中的电流流动。 锁存器的输入节点电容耦合到信号源，节点上的直流电压由偏置电路设置。