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公开(公告)号：US20240276124A1
公开(公告)日：2024-08-15
申请号：US18167665
申请日：2023-02-10
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Shan Chen , Hiroaki Ebihara , Rui Wang , Zhenfu Tian
Abstract: A local ramp buffer includes a deep N− well layer disposed in a P− substrate beneath a surface of the P− substrate, a P− well disposed between the surface of the P− substrate and the deep N− well layer, and an N− well structure disposed in the P− substrate and coupled to the deep N− well layer. The N− well structure is disposed between the surface of the P− substrate and the deep N− well layer. The P− well is disposed inside an opening in the N− well structure. The N− well structure and the deep N− well layer are configured to isolate the P− well within the opening. A source follower transistor is disposed in the P− well. The source follower transistor includes a gate terminal coupled to the N− well structure and a ramp generator.
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公开(公告)号：US11968468B2
公开(公告)日：2024-04-23
申请号：US17659045
申请日：2022-04-13
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara , Zhenfu Tian , Peter Bartkovjak , Satoshi Sakurai
IPC: H04N25/772 , H03K5/24 , H03M1/12 , H03M1/56 , H04N17/00 , H04N25/709 , H04N25/75
CPC classification number: H04N25/772 , H03K5/24 , H03M1/1245 , H03M1/56 , H04N17/002 , H04N25/709 , H04N25/75
Abstract: A ramp buffer circuit includes a ramp buffer input device having an input coupled to receive a ramp signal. A current monitor is circuit coupled to a power line and the ramp buffer input device to generate a current monitor signal in response to an input current conducted through the ramp buffer input device. A corner bias circuit is coupled to the current monitor circuit to generate an assist bias voltage in response to the current monitor signal. A bias current source is coupled to an output of the ramp buffer input device. An assist current source is coupled to the corner bias circuit and coupled between the output of the ramp buffer input device and ground to conduct an assist current from the output of the ramp buffer input device to ground in response to the assist bias voltage.
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公开(公告)号：US20210358994A1
公开(公告)日：2021-11-18
申请号：US17066277
申请日：2020-10-08
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Sang Joo Lee , Rui Wang , Hiroaki Ebihara , Tiejun Dai , Hiroki Ui
IPC: H01L27/146 , H01L27/148 , H04N5/378
Abstract: A pixel array includes pixel cells disposed in semiconductor material. Each of the pixel cells includes photodiodes, and a floating diffusion to receive image charge from the photodiodes. A source follower is coupled to the floating diffusion to generate an image signal in response image charge from the photodiodes. Drain regions of first and second row select transistors are coupled to a source of the source follower. A common junction is disposed in the semiconductor material between gates of the first and second row select transistors such that the drains of the first and second row select transistors are shared and coupled together through the semiconductor material of the common junction. The pixel cells are organized into a rows and columns with bitlines.
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公开(公告)号：US20200295739A1
公开(公告)日：2020-09-17
申请号：US16352673
申请日：2019-03-13
Applicant: OmniVision Technologies, Inc.
Inventor： Liang Zuo , Rui Wang , Hiroaki Ebihara , Nijun Jiang
Abstract: A ramp generator includes an integrator including a first stage having first and second inputs and first and second outputs, and a second stage including first and second transistors coupled between a power supply rail and ground. A node between the first and second transistors is coupled to the output of the integrator amplifier. A control terminal of the first transistor is coupled to the first output of the first stage, and a control terminal of the second transistor is coupled to the second output of the first stage. A first current flows from the output to ground during a ramp event in the ramp signal generated from the output. Trimming circuitry is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to trimming inputs. The second current substantially matches the first current.
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35.发明授权公开(公告)号：US10431608B2
公开(公告)日：2019-10-01
申请号：US15486896
申请日：2017-04-13
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara
IPC: H01L27/12 , H04N5/378 , H04N5/3745
Abstract: Example comparators as discussed herein may include a second stage coupled to provide an output in response to an intermediate voltage, a first stage coupled to provide the intermediate voltage in response to an input. The first stage including a pair of cascode devices coupled to a current mirror, a low gain input coupled to inputs of the first stage via first switches, and further selectively coupled to the pair of cascode devices via second switches, and a high gain input coupled to the first and second inputs of the first stage via the first switches, and further selectively coupled to the pair of cascode devices via fourth switches. Based on a low conversion gain mode, the low gain input may be coupled to the inputs by the first switches, and further coupled to the pair of cascode devices by the second switches in response to a control signal being in a first state, and based on a high conversion gain mode, the high gain input may be coupled to the first and second inputs by the first switches, and further coupled to the pair of cascode device by the fourth switch in response to the control signal being in a second state.
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Patent Agency Ranking
公开(公告)号：US10263031B2
公开(公告)日：2019-04-16
申请号：US15421911
申请日：2017-02-01
Applicant: OmniVision Technologies, Inc.
Inventor： Rui Wang , Hiroaki Ebihara , Zheng Yang , Chun-Ming Tang , Chao-Fang Tsai , Tiejun Dai
IPC: H01J40/14 , H01L27/146 , H04N5/3745 , H04N5/369
Abstract: A hybrid-bonded image sensor has a photodiode die with multiple macrocells; each macrocell has at least one photodiode and a coupling region. The coupling regions couple to a coupling region of a macrocell unit of a supporting circuitry die where they feed an input of an amplifier and a feedback capacitor. The feedback capacitor also couples to output of the amplifier, and the amplifier inverts between the input and the output. The method includes resetting a photodiode of the photodiode die; coupling signal from photodiode through the bond point to the supporting circuitry die to a feedback capacitor and to an input of the amplifier, the feedback capacitor also coupled to an inverting output of the amplifier; and amplifying the signal with the amplifier, where a capacitance of the feedback capacitor determines a gain of the amplifier.
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公开(公告)号：US10171765B1
公开(公告)日：2019-01-01
申请号：US15853508
申请日：2017-12-22
Applicant: OmniVision Technologies, Inc.
Inventor： Hiroaki Ebihara , Xueqing Wang
IPC: H04N5/374 , H04N5/235 , H01L27/146 , H04N5/378
Abstract: A photodiode is adapted to accumulate image charges. A transfer transistor transfers the image charges to the floating diffusion. A source follower transistor is coupled to receive the voltage of the floating diffusion and provide an amplified signal. A row select transistor enables the amplified signal and outputs the amplified signal to a bitline. A first current source generator is coupled between the bitline and a ground. The first current source generator sinks current through a first cascode transistor, a first bias transistor and a second bias transistor. The first cascode transistor is biased by a cascode control voltage. The first bias transistor and the second bias transistor are biased by a bias control voltage.
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公开(公告)号：US20180302579A1
公开(公告)日：2018-10-18
申请号：US15485534
申请日：2017-04-12
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Sohei Manabe , Keiji Mabuchi , Takayuki Goto , Duli Mao , Hiroaki Ebihara , Kazufumi Watanabe
IPC: H04N5/355 , H04N5/378 , H04N5/3745 , H01L27/146
CPC classification number: H04N5/3559 , H01L27/14609 , H01L27/1461 , H01L27/14612 , H01L27/14634 , H01L27/14636 , H01L27/14643 , H04N5/37452 , H04N5/378
Abstract: A pixel circuit for use in a high dynamic range (HDR) image sensor includes a photodiode and a floating diffusion is disposed in the first semiconductor wafer. A transfer transistor is disposed in the first semiconductor wafer and is adapted to be switched on to transfer the charge carriers photogenerated in the photodiode to the floating diffusion. An in-pixel capacitor is disposed in a second semiconductor wafer. The first semiconductor wafer is stacked with and coupled to the second semiconductor wafer. A dual floating diffusion (DFD) transistor is disposed in the first semiconductor wafer. The in-pixel capacitor is selectively coupled to the floating diffusion through the DFD transistor. The floating diffusion is set to low conversion gain in response to the in-pixel capacitor being coupled to the floating diffusion, and high conversion gain in response to the in-pixel capacitor being decoupled from the floating diffusion.
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公开(公告)号：US09967505B1
公开(公告)日：2018-05-08
申请号：US15486815
申请日：2017-04-13
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara
CPC classification number: H04N5/378 , H03K5/2472 , H03K5/2481 , H03M1/56 , H04N5/374
Abstract: Example comparators as disclosed herein may include a first comparator comprising a first plurality of device areas, wherein the first plurality of device areas at least includes a first comparator input device area, a first comparator cascode device area, and a first comparator current mirror area, and a second comparator comprising a second plurality of device areas, wherein the second plurality of device areas at least includes a second comparator input device area, a second comparator cascode device area, and a second comparator current mirror area, where the second comparator input area is disposed between the first comparator input area and the first comparator cascode device area, the first comparator cascode device area is disposed between the second comparator input area and the second comparator cascode device area, the first comparator current mirror area is disposed between the first comparator cascode device area and the second comparator current mirror area, the second comparator cascode device area is disposed between the first comparator cascode device area and the second comparator current mirror area, and the second comparator current mirror area is disposed between the first comparator current mirror area and a second comparator second stage input area.
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公开(公告)号：US09762825B2
公开(公告)日：2017-09-12
申请号：US14985122
申请日：2015-12-30
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara
Abstract: A method for reducing ADC time for dark signals starts with pixel array capturing image data of frames including first frame and second frame. Pixel array includes visible pixels and black pixels (OPB). Scanning circuitry then selects OPB of first frame to be readout. OPB generate a dark signal when selected by scanning circuitry. Column readout circuitry included in readout circuitry then acquires the dark signal of first frame and processes the dark signal based on a ramp signal received from ramp generator included in readout circuitry to generate dark ADC output. Readout circuitry then determines a ramp timing offset based on the dark signal of first frame. The ramp timing offset is then applied to the second frame, which includes generating by the ramp generator the ramp signal for a second frame that includes the ramp timing offset. Other embodiments are described.
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