公开(公告)号：US20150340391A1

公开(公告)日：2015-11-26

申请号：US14286478

申请日：2014-05-23

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster

IPC: H01L27/146 ,  H04N5/378

CPC classification number: H01L27/14605 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14649 ,  H04N5/378

Abstract: An image sensor includes a photodiode disposed in semiconductor material to accumulate image charge in response to light directed through a back side of the semiconductor material. A scattering structure is disposed proximate to the front side of the semiconductor material such that the light that is directed into the semiconductor material through the back side is scattered back through the photodiode. A deep trench isolation structure is disposed in the semiconductor material that isolates the photodiode and defines an optical path such that the light that is scattered back through the photodiode in the optical path is totally internally reflected by the DTI. An antireflective coating is disposed on the back side of the semiconductor material and totally internally reflects the light scattered by the scattering structure to confine the light to remain in the optical path until it is absorbed.

Abstract translation: 图像传感器包括设置在半导体材料中的光电二极管，以响应于通过半导体材料的背面的光而积累图像电荷。 散射结构靠近半导体材料的正面设置，使得通过背面引导到半导体材料中的光被散射回到光电二极管。 深沟槽隔离结构设置在半导体材料中，隔离光电二极管并限定光路，使得通过光路中的光电二极管散射的光被DTI完全内部反射。 防反射涂层设置在半导体材料的背面，并且全部内部反射由散射结构散射的光，以将光限制在光路中，直到被吸收。

公开(公告)号：US20150303235A1

公开(公告)日：2015-10-22

申请号：US14255535

申请日：2014-04-17

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Dajiang Yang ,  Gang Chen ,  Zhenhong Fu ,  Duli Mao ,  Eric A. G. Webster ,  Sing-Chung Hu ,  Dyson H. Tai

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14612 ,  H01L27/14614 ,  H01L27/14689

Abstract: A pixel cell includes a storage transistor disposed in a semiconductor substrate. The storage transistor includes a storage gate disposed over the semiconductor substrate, and a storage gate implant that is annealed and has a gradient profile in the semiconductor substrate under the storage transistor gate to store image charge accumulated by a photodiode disposed in the semiconductor substrate. A transfer transistor is disposed in the semiconductor substrate and is coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor. The transfer transistor includes a transfer gate disposed over the semiconductor substrate. An output transistor is coupled to an output of the storage transistor to selectively transfer the image charge from the storage transistor to a read out node. The output transistor includes an output gate disposed over the semiconductor substrate.

Abstract translation: 像素单元包括设置在半导体衬底中的存储晶体管。 存储晶体管包括设置在半导体衬底上的存储栅极，以及在存储晶体管栅极下的半导体衬底中退火并具有梯度分布的存储栅极注入，以存储由设置在半导体衬底中的光电二极管累积的图像电荷。 传输晶体管设置在半导体衬底中并耦合在光电二极管和存储晶体管的输入端之间，以选择性地将图像电荷从光电二极管转移到存储晶体管。 转移晶体管包括设置在半导体衬底上的转移栅极。 输出晶体管耦合到存储晶体管的输出，以选择性地将图像电荷从存储晶体管传送到读出节点。 输出晶体管包括设置在半导体衬底上的输出门。

公开(公告)号：US20150200314A1

公开(公告)日：2015-07-16

申请号：US14156053

申请日：2014-01-15

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Eric A. G. Webster

IPC: H01L31/0352 ,  H01L27/146 ,  H01L31/09 ,  H01L31/107

CPC classification number: H01L27/1464 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636

Abstract: A single photon avalanche diode (SPAD) includes an n doped epitaxial layer disposed in a first semiconductor layer. A p doped epitaxial layer is above the n doped epitaxial layer on a back side of the first semiconductor layer. A multiplication junction is defined at an interface between the n doped epitaxial layer and the p doped epitaxial layer. A multiplication junction is reversed biased above a breakdown voltage such that a photon received through the back side of the first semiconductor layer triggers an avalanche multiplication process in the multiplication junction. A p− doped guard ring region is implanted in the n doped epitaxial layer surrounding the multiplication junction.

Abstract translation: 单光子雪崩二极管（SPAD）包括设置在第一半导体层中的n掺杂外延层。 p掺杂的外延层在第一半导体层的背面上的n掺杂的外延层之上。 在n掺杂外延层和p掺杂外延层之间的界面处限定一个乘法结。 乘法结被反向偏置在击穿电压之上，使得通过第一半导体层的背面接收的光子在乘法结中触发雪崩倍增处理。 p掺杂的保护环区域被注入围绕乘法结的n掺杂外延层中。