公开(公告)号：US06434582B1

公开(公告)日：2002-08-13

申请号：US09336394

申请日：1999-06-18

Applicant: Gwangwoo Choe ,  James R. MacDonald

Inventor： Gwangwoo Choe ,  James R. MacDonald

IPC: G06F102

CPC classification number: G06F7/5446

Abstract: A system and method for computing the cosine of an input value. The system comprises a logical processing unit and an addition unit. The logical processing unit comprises an input bus with a plurality of input lines for receiving an input angle value. The logical processing unit includes a first plurality of gates, preferably AND gates, coupled to the input bus. Each gate of the first plurality of gates couples to two or more of the input lines. The logical processing unit generates N output operands on N corresponding output buses. At least one of the output buses includes (a) at least one output line coupled to an output of one of the first plurality of gates, and (b) at least one output line coupled to one of the input lines of the input bus. The number N of output buses is greater than or equal to two. The addition unit couples to the N output buses of the logical processing unit, and is configured to perform an addition of the N binary operands provided on the N output buses. The addition unit generates a resultant number which represents the cosine of the input operand conveyed on the input bus. The input angle value is assumed to have a predetermined number of leading zeros. In general, output lines are coupled to (a) input lines, (b) outputs of gates, or (c) set equal to zero.

Abstract translation: 用于计算输入值的余弦的系统和方法。 该系统包括逻辑处理单元和加法单元。 逻辑处理单元包括具有用于接收输入角度值的多条输入线的输入总线。 逻辑处理单元包括耦合到输入总线的第一多个门，优选与门。 第一多个门的每个栅极耦合到两个或更多个输入线。 逻辑处理单元在N个对应的输出总线上产生N个输出操作数。 输出总线中的至少一个包括（a）耦合到第一多个门中的一个的输出的至少一个输出线，以及（b）耦合到输入总线的输入线之一的至少一个输出线。 输出总线数N大于或等于2。 加法单元耦合到逻辑处理单元的N个输出总线，并且被配置为执行在N个输出总线上提供的N个二进制操作数的相加。 加法单元生成表示在输入总线上传送的输入操作数的余弦的合成数。 假设输入角度值具有预定数量的前导零。 通常，输出线耦合到（a）输入线，（b）门的输出，或（c）设置为等于零。

公开(公告)号：US6044430A

公开(公告)日：2000-03-28

申请号：US992283

申请日：1997-12-17

Applicant: James R. MacDonald

Inventor： James R. MacDonald

IPC: G06F9/48 ,  G06F12/12 ,  G06F9/46

CPC classification number: G06F9/4812 ,  G06F12/126

Abstract: A CPU includes a real time interrupt (RTI) control unit configured to control real time interrupt capabilities of the CPU. Upon receipt of a real time interrupt signal via an RTI pin, the RTI control unit interrupts the currently executing instructions at an instruction boundary in order to execute the interrupt service routine. Instead of using the interrupt acknowledge cycles normally used to locate an interrupt vector, and then using the interrupt vector to locate an interrupt descriptor, the interrupt descriptor is stored in an RTI register coupled to the RTI control unit. In one embodiment, the CPU is configured not to save processor context upon initiation of a real time interrupt. Instead, as register resources are needed by the real time service routine, these resources are allocated. Registers allocated for real time use are indicated in the RTI register. In yet another embodiment, the CPU is configured with lockable cache lines in the instruction and data caches. An RTI bit is defined in the code and data segment descriptors for indicating whether or not the code/data within the segment is real time code/data (i.e. is used in an RTI service routine). The code/data within these segments is locked into the instruction and/or data cache. The cache replacement algorithm employed by the cache attempts to select a non-locked cache line for storing a cache line being transferred into the cache.

Abstract translation: CPU包括被配置为控制CPU的实时中断能力的实时中断（RTI）控制单元。 在RTI接收到实时中断信号时，RTI控制单元在指令边界处中断当前正在执行的指令，以执行中断服务程序。 而不是使用通常用于定位中断向量的中断确认周期，然后使用中断向量来定位中断描述符，中断描述符被存储在连接到RTI控制单元的RTI寄存器中。 在一个实施例中，CPU被配置成在启动实时中断时不保存处理器上下文。 相反，由于实时服务程序需要注册资源，所以分配这些资源。 分配给实时使用的寄存器在RTI寄存器中指示。 在另一个实施例中，CPU在指令和数据高速缓存中配置有可锁定的高速缓存行。 在代码和数据段描述符中定义了一个RTI位，用于指示段内的代码/数据是否是实时代码/数据（即在RTI服务程序中使用）。 这些段中的代码/数据被锁定在指令和/或数据高速缓存中。 缓存器采用的高速缓存替换算法尝试选择非锁定高速缓存线，用于存储被传送到高速缓存中的高速缓存行。

公开(公告)号：US5790783A

公开(公告)日：1998-08-04

申请号：US623020

申请日：1996-03-28

Applicant: Sherman Lee ,  James R. MacDonald ,  Michael T. Wisor

Inventor： Sherman Lee ,  James R. MacDonald ,  Michael T. Wisor

IPC: G06F1/00 ,  G06F11/00 ,  G06F21/00 ,  G06F12/14

CPC classification number: G06F11/006 ,  G06F21/12 ,  G06F21/73 ,  G06F2207/7219 ,  G06F2211/007

Abstract: A method and apparatus for providing, maintaining and upgrading the software lock of a microprocessor. When a processor upgrade occurs, software that was serialized to the previously installed processor detects that it is running on an unauthorized processor. The software initiates a reauthorization process based on a reauthorization use profile. The temporary re-enabling of the software is allowed if the authorization service is not available.

Abstract translation: 一种用于提供，维护和升级微处理器的软件锁的方法和装置。 当处理器升级发生时，序列化到先前安装的处理器的软件会检测到它在未经授权的处理器上运行。 该软件基于重新授权使用配置文件启动重新授权过程。 如果授权服务不可用，则允许软件的临时重新启用。

公开(公告)号：US5790663A

公开(公告)日：1998-08-04

申请号：US623021

申请日：1996-03-28

Applicant: Sherman Lee ,  James R. MacDonald ,  Michael T. Wisor

Inventor： Sherman Lee ,  James R. MacDonald ,  Michael T. Wisor

IPC: G06F12/14 ,  G06F11/00 ,  G06F21/00 ,  G06F21/22 ,  G06F21/24 ,  H04L9/00 ,  H04L9/32

CPC classification number: G06F21/73 ,  G06F11/006 ,  G06F12/1408 ,  G06F2207/7219 ,  G06F2211/007

Abstract: A method and apparatus for software to access a microprocessor serial number. Provision of the serial number allows the manufacturer better control over its product and also permits software vendors to register their products. The serial number is encrypted using a pair of encryption keys to prevent unauthorized changes. At least one of the encryption keys is itself encoded to prevent unauthorized access, while permitting software to access the serial number.

Abstract translation: 一种用于访问微处理器序列号的软件的方法和装置。 提供序列号允许制造商更好地控制其产品，并允许软件供应商注册其产品。 使用一对加密密钥对序列号进行加密，以防止未经授权的更改。 至少有一个加密密钥本身被编码以防止未经授权的访问，同时允许软件访问序列号。

公开(公告)号：US4883600A

公开(公告)日：1989-11-28

申请号：US256541

申请日：1988-10-12

Applicant: James R. MacDonald ,  Barbara E. Fair

Inventor： James R. MacDonald ,  Barbara E. Fair

IPC: C02F1/76 ,  C02F5/12

CPC classification number: C02F5/12 ,  C02F1/76 ,  C02F1/766

Abstract: The soluble manganese species can be maintained in aqueous systems in the presence of halogen species by treating the waters with certain water-soluble, nitrogen containing compositions.

Abstract translation: 通过用某些水溶性含氮组合物处理水，可以在卤素物质的存在下将可溶性锰物质保持在含水体系中。

公开(公告)号：US08572420B2

公开(公告)日：2013-10-29

申请号：US11071961

申请日：2005-03-04

Applicant: Drew J. Dutton ,  James R. MacDonald ,  Henry Wurzburg

Inventor： Drew J. Dutton ,  James R. MacDonald ,  Henry Wurzburg

IPC: G06F3/00

CPC classification number: G06K19/07732 ,  G06K7/0013 ,  G06K7/0086 ,  G06K19/0701

Abstract: In various embodiments, a computer system may include a computer controller to send and/or receive sideband signals to/from a USB device. In some embodiments, the USB device may include a USB controller to send/receive sideband signals to/from the computer controller. The computer controller and USB controller may allow communications between the computer system and the USB device when either of the computer system or USB device is in a low power state. The sideband signal sent between the computer system and the USB device may trigger the other of the computer system or USB device to enter a normal power state. In some embodiments, the computer controller and/or USB controller may be further coupled to a memory to buffer data to be sent to the computer system or USB device after the computer system or USB device returns to a normal power state.

Abstract translation: 在各种实施例中，计算机系统可以包括计算机控制器来向/从USB设备发送和/或接收边带信号。 在一些实施例中，USB设备可以包括用于向计算机控制器发送/接收边带信号的USB控制器。 当计算机系统或USB设备中的任一个处于低功率状态时，计算机控制器和USB控制器可以允许计算机系统和USB设备之间的通信。 在计算机系统和USB设备之间发送的边带信号可能触发计算机系统或USB设备中的另一个进入正常的电源状态。 在一些实施例中，计算机控制器和/或USB控制器可以进一步耦合到存储器，以在计算机系统或USB设备恢复到正常功率状态之后缓冲要发送到计算机系统或USB设备的数据。

公开(公告)号：US06385632B1

公开(公告)日：2002-05-07

申请号：US09336393

申请日：1999-06-18

Applicant: Gwangwoo Choe ,  James R. MacDonald

Inventor： Gwangwoo Choe ,  James R. MacDonald

IPC: G06F102

CPC classification number: G06F7/5446

Abstract: A system and method for evaluating one or more functions using a succession of CORDIC stages/iterations followed by a residual rotation. The succession of CORDIC stages are preferably partitioned into (a) a Z path which operates on an input angle and generates an output angle, and (b) an X/Y path which operates on an input point and generates an output point. The residual rotation rotates the output point by the output angle to generate a resultant point using a small angle approximation for sine and an accurate evaluation for sine of the output angle. The number of CORDIC stages in the succession is chosen so that the error in the coordinates of the resultant point induced by the approximation of sine is smaller than a desired amount. In particular, the number of CORDIC stages in the succession is chosen to be greater than or equal to (N+1)/3 in order to guarantee N bits of precision in coordinates of the resultant point. The Z path has a propagation time which is smaller than the X/Y path. This allows the cosine computation unit to generate the cosine of the output angle prior to the time when the X/Y path generates the output point. Thus, the residual rotation may be performed immediately upon generation of the output point.

Abstract translation: 一种使用一系列CORDIC阶段/迭代跟随剩余旋转来评估一个或多个功能的系统和方法。 CORDIC级的连续优选被划分为（a）在输入角度上操作并产生输出角的Z路径，以及（b）在输入点上操作并产生输出点的X / Y路径。 剩余旋转将输出点旋转输出角度，以使用正弦近似的小角度和对输出角度的正弦值进行准确评估来产生合成点。 选择连续的CORDIC级的数量，使得由正弦近似引起的结果点的坐标误差小于期望的量。 特别地，为了保证所得点的坐标精度N位，将连续的CORDIC级数选择为大于或等于（N + 1）/ 3。 Z路径的传播时间小于X / Y路径。 这允许余弦计算单元在X / Y路径产生输出点之前产生输出角度的余弦值。 因此，可以在产生输出点时立即执行残余旋转。

公开(公告)号：US06295574B1

公开(公告)日：2001-09-25

申请号：US09488158

申请日：2000-01-20

Applicant: James R. MacDonald

Inventor： James R. MacDonald

IPC: G06F946

CPC classification number: G06F9/4812 ,  G06F12/126

Abstract: A CPU includes a real time interrupt (RTI) control unit configured to control real time interrupt capabilities of the CPU. Upon receipt of a real time interrupt signal via an RTI pin, the RTI control unit interrupts the currently executing instructions at an instruction boundary in order to execute the interrupt service routine. Instead of using the interrupt acknowledge cycles normally used to locate an interrupt vector, and then using the interrupt vector to locate an interrupt descriptor, the interrupt descriptor is stored in an RTI register coupled to the RTI control unit. In one embodiment, the CPU is configured not to save processor context upon initiation of a real time interrupt. Instead, as register resources are needed by the real time service routine, these resources are allocated. Registers allocated for real time use are indicated in the RTI register. In yet another embodiment, the CPU is configured with lockable cache lines in the instruction and data caches. An RTI bit is defined in the code and data segment descriptors for indicating whether or not the code/data within the segment is real time code/data (i.e. is used in an RTI service routine). The code/data within these segments is locked into the instruction and/or data cache. The cache replacement algorithm employed by the cache attempts to select a non-locked cache line for storing a cache line being transferred into the cache.

Abstract translation: CPU包括被配置为控制CPU的实时中断能力的实时中断（RTI）控制单元。 在RTI接收到实时中断信号时，RTI控制单元在指令边界处中断当前正在执行的指令，以执行中断服务程序。 而不是使用通常用于定位中断向量的中断确认周期，然后使用中断向量来定位中断描述符，中断描述符被存储在连接到RTI控制单元的RTI寄存器中。 在一个实施例中，CPU被配置成在启动实时中断时不保存处理器上下文。 相反，由于实时服务程序需要注册资源，所以分配这些资源。 分配给实时使用的寄存器在RTI寄存器中指示。 在另一个实施例中，CPU在指令和数据高速缓存中配置有可锁定的高速缓存行。 在代码和数据段描述符中定义了一个RTI位，用于指示段内的代码/数据是否是实时代码/数据（即在RTI服务程序中使用）。 这些段中的代码/数据被锁定在指令和/或数据高速缓存中。 缓存器使用的高速缓存替换算法尝试选择非锁定高速缓存行来存储被传送到高速缓存中的高速缓存行。

公开(公告)号：US5799203A

公开(公告)日：1998-08-25

申请号：US649537

申请日：1996-05-17

Applicant: Sherman Lee ,  James R. MacDonald ,  Michael T. Wisor

Inventor： Sherman Lee ,  James R. MacDonald ,  Michael T. Wisor

IPC: G06F11/22 ,  G06F15/177 ,  G06F13/00

CPC classification number: G06F9/4411 ,  G06F11/2289 ,  G06F15/177

Abstract: A system and method for providing information regarding system support capabilities to a processor. A computer system includes a processing unit, a main memory and a first plurality of peripherals coupled to a first bus. A bus bridge couples the first bus to a second bus and a second plurality of support peripherals are coupled to the second bus. The processing unit is capable of providing requests for system support information to the bus bridge and the first and second plurality support peripherals. The peripherals are configured to provide responses to the request. The processing unit stores the responses and uses the information received to enable and disable its functional units or the peripheral's functional units accordingly. In one embodiment, the requests and information are provided along a dedicated serial interface. In another, the requests and information are provided as specialized bus cycles along the CPU bus.

Abstract translation: 一种用于向处理器提供关于系统支持能力的信息的系统和方法。 计算机系统包括处理单元，主存储器和耦合到第一总线的第一多个外围设备。 总线桥将第一总线耦合到第二总线，并且第二多个支持外围设备耦合到第二总线。 处理单元能够向总线桥以及第一和第二多个支持外围设备提供系统支持信息的请求。 外设被配置为提供对请求的响应。 处理单元存储响应并使用所接收的信息来相应地启用和禁用其功能单元或外围设备的功能单元。 在一个实施例中，沿着专用串行接口提供请求和信息。 另一方面，请求和信息作为沿CPU总线的专用总线周期提供。

公开(公告)号：US5320967A

公开(公告)日：1994-06-14

申请号：US53861

申请日：1993-04-20

Applicant: Stanley C. Avallone ,  Roger W. Fowee ,  James R. MacDonald ,  Nicholas J. Furibondo

Inventor： Stanley C. Avallone ,  Roger W. Fowee ,  James R. MacDonald ,  Nicholas J. Furibondo

IPC: G01M3/04 ,  F22B37/42 ,  G01M3/20 ,  G01M3/22 ,  G01N33/18 ,  G01N35/02

CPC classification number: G01N33/18 ,  F22B37/421 ,  G01M3/226 ,  Y10S252/964 ,  Y10T436/115831 ,  Y10T436/12

Abstract: Leakage of water from a boiler water system wherein steam is generated in a boiler from feedwater fed to the boiler, and the concentration of impurities in the boiler water within the boiler is reduced by withdrawing fractions thereof as blowdown while admitting additional feedwater as boiler-water makeup, is determined. The boiler has a concentration cycle value, the concentration cycle value being the average value of the concentration of an inert component in the blowdown at steady state (C.sub.F) divided by the concentration of the inert component in the feedwater (C.sub.I). The concentration of the inert component in the boiler at steady state varies from a high concentration C.sub.H, having a value that is higher than C.sub.F, to a low concentration C.sub.L, having a value between the (C.sub.I) and the (C.sub.F), within a time period. The method comprises:employing as the inert component an inert tracer;sensing a characteristic of the inert tracer in the boiler at steady state equivalent to its concentration in the boiler water;converting the sensed characteristic to a value equivalent to the concentration of the inert tracer in the boiler water; andactivation of a signal when a variance in the cyclic concentration fluctuation of said inert tracer occurs that is consistent with a leakage of boiler water.

Abstract translation: 来自锅炉水系统的水的泄漏，其中在锅炉中从供给到锅炉的给水中产生蒸汽，并且通过将其作为排放物的馏分取出而将锅炉水中的杂质浓度降低，同时允许另外的给水作为锅炉水 化妆，确定。 锅炉具有浓度循环值，浓度循环值是在稳定排放（CF）中的惰性组分的浓度除以给水（CI）中的惰性组分的浓度的平均值。 在稳定状态下锅炉中的惰性组分的浓度从具有高于CF的高浓度CH与具有（CI）和（CF）之间的值的低浓度CL在一个 时间段。 该方法包括：将惰性组分用作惰性示踪剂; 感测锅炉中惰性示踪剂的特性，其稳定状态等于其在锅炉水中的浓度; 将感测特性转换成与锅炉水中的惰性示踪剂的浓度相当的值; 当所述惰性示踪剂的循环浓度波动的变化发生与锅炉水的泄漏一致时，激活信号。