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    Voice and data exchange over a packet based network with timing recovery
    32.
    发明授权
    Voice and data exchange over a packet based network with timing recovery 有权

    公开(公告)号：US06549587B1

    公开(公告)日：2003-04-15

    申请号：US09493458

    申请日：2000-01-28

    Applicant: Henry Li

    Inventor： Henry Li

    IPC: H04L2714

    CPC classification number: H04L65/1026 ,  H04B3/23 ,  H04B3/234 ,  H04L7/0278 ,  H04L12/2801 ,  H04L12/66 ,  H04L29/06027 ,  H04L65/1036 ,  H04L65/1069 ,  H04L65/80 ,  H04M7/125

    Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

    Low power serial protocol translator for use in multi-circuit board electronic systems
    33.
    发明授权
    Low power serial protocol translator for use in multi-circuit board electronic systems 失效

    公开(公告)号：US5878234A

    公开(公告)日：1999-03-02

    申请号：US710024

    申请日：1996-09-10

    Applicant: Marek Dutkiewicz ,  Henry Li

    Inventor： Marek Dutkiewicz ,  Henry Li

    IPC: G06F13/42 ,  H04L12/40 ,  H04L12/413 ,  G06F13/00

    CPC classification number: H04L12/40 ,  G06F13/423 ,  Y02B60/1228 ,  Y02B60/1235

    Abstract: A low power reduced size serial device protocol translator including a slave controller and detection circuit for detecting start and stop conditions on serial data (SDA) and serial clock (SCL) lines in a serial communication system is described. The start and stop condition detector includes two flip-flops; one for providing a signal that indicates when a start condition has occurred on the SDA and SCL lines and another for indicating when a stop condition has occurred. Each of the flip-flops have their data inputs coupled to a high logic level and their enable input coupled to the serial clock line. The first flip-flop for indicating the start condition has its clock input coupled to the inverse of the serial data signal and the second flip-flop for indicating the stop condition has its clock input directly coupled to the serial data signal. As a result, the first and second flip-flops are only enabled and clocked when either a start or stop condition is occurring, resulting in an extremely low power slave controller detection system. The translator of the present invention translates serial signals between slave and master devices having different protocol types. The translator utilizes sub-protocol signals including length information corresponding to the number of data bits being transmitted to the slave device. The translator uses the length information to gate the serial data from the master device to the slave device. The translator allows for reduction of physical interconnections in a master/slave system in which a master devices resides on a first printed circuit board (PCB) and communicates with slave devices on a second PCB having more than one type of serial communication protocol. In this case, the translator resides on the same PCB as the slave devices thus requiring that only the serial buses corresponding to the master device protocol type be physically coupled across the two PCB's interconnection interface.

    Interactive multilingual word-alignment techniques
    34.
    发明授权
    Interactive multilingual word-alignment techniques 有权
    交互式多语言字对齐技术

    公开(公告)号：US08930176B2

    公开(公告)日：2015-01-06

    申请号：US12753023

    申请日：2010-04-01

    Applicant: Henry Li ,  Matthew Robert Scott ,  Xiaohua Liu ,  Hao Wei ,  Ming Zhou

    Inventor： Henry Li ,  Matthew Robert Scott ,  Xiaohua Liu ,  Hao Wei ,  Ming Zhou

    IPC: G06F17/28

    CPC classification number: G06F17/2827 ,  G06F17/2854

    Abstract: Techniques for interactively presenting word-alignments of multilingual translations and automatically improving those translations based upon user feedback are described herein. With one or more implementations of the techniques described herein, a word-alignment user-interface (UI) concurrently displays a pair of bilingual sentences, where one is a translation of the other, and interactively highlights linked (i.e., “word-aligned”) words and phrases of the pair. Other implementations of the techniques described herein offer an option for a user to provide feedback about the existing word-alignments or realign the words or phrases. In still other described implementations, word-alignment is automatically improved based upon that user feedback.

    Abstract translation: 本文描述了用于交互地呈现多语言翻译的字对齐并基于用户反馈自动改进这些翻译的技术。 通过本文描述的技术的一个或多个实现，字对齐用户界面（UI）同时显示一对双语句子，其中一个是另一个的翻译，并且交互地突出显示链接（即，“字对齐” ）该对的单词和短语。 本文描述的技术的其他实施方案提供了用于用户提供关于现有单词对齐或重新对准单词或短语的反馈的选项。 在其他描述的实施方式中，基于该用户反馈自动改进字对齐。

    Method and system for a gigabit Ethernet IP telephone chip with integrated DDR interface
    37.
    发明授权
    Method and system for a gigabit Ethernet IP telephone chip with integrated DDR interface 有权
    具有集成DDR接口的千兆以太网IP电话芯片的方法和系统

    公开(公告)号：US07929518B2

    公开(公告)日：2011-04-19

    申请号：US11151139

    申请日：2005-06-13

    Applicant: Paul Shore ,  Balwinder Boora ,  Henry Li ,  Stephen Mueller

    Inventor： Paul Shore ,  Balwinder Boora ,  Henry Li ,  Stephen Mueller

    IPC: H04L12/66 ,  G06F3/00

    CPC classification number: H04L63/08 ,  H04L47/10 ,  H04L47/2416 ,  H04L47/2433 ,  H04L47/2441 ,  H04L47/6215 ,  H04L49/352 ,  H04L49/355 ,  H04M1/2535 ,  H04M1/6033 ,  H04W88/02

    Abstract: Methods and systems for processing data are disclosed herein and may comprise processing data via a single gigabit Ethernet IP telephone chip integrated within a gigabit Ethernet IP telephone. At least a portion of the processed data may be communicated to an off-chip DDR memory within the gigabit IP telephone via an on-chip DDR memory interface integrated within the gigabit IP telephone chip. The data may be acquired from the off-chip DDR memory via the DDR memory interface for the processing. A request to process the data may be received by the gigabit Ethernet IP telephone chip. The request for processing the data may comprise a Memory Read command, a Memory Write command, a Memory Write with Reply command, a Memory Swap command, an Input/Output (I/O) Read command, an I/O Write command, and/or an I/O Write with Reply command.

    Abstract translation: 用于处理数据的方法和系统在本文中公开，并且可以包括通过集成在千兆比特以太网IP电话中的单个千兆以太网IP电话芯片来处理数据。 经处理的数据的至少一部分可以经由集成在千兆位IP电话芯片内的片上DDR存储器接口传送到千兆IP电话内的片外DDR存储器。 可以通过用于处理的DDR存储器接口从片外DDR存储器获取数据。 处理数据的请求可以由千兆以太网IP电话芯片接收。 处理数据的请求可以包括存储器读取命令，存储器写入命令，具有回复的存储器写入命令，存储器交换命令，输入/输出（I / O）读取命令，I / O写入命令和 /或I / O Write with Reply命令。

    Method and system for a gigabit ethernet IP telephone chip with 802.1p and 802.1Q quality of service (QoS) functionalities
    38.
    发明授权
    Method and system for a gigabit ethernet IP telephone chip with 802.1p and 802.1Q quality of service (QoS) functionalities 有权
    具有802.1p和802.1Q服务质量（QoS）功能的千兆以太网IP电话芯片的方法和系统

    公开(公告)号：US07864681B2

    公开(公告)日：2011-01-04

    申请号：US11151135

    申请日：2005-06-13

    Applicant: Paul Shore ,  Balwinder Boora ,  Henry Li ,  Stephen Mueller

    Inventor： Paul Shore ,  Balwinder Boora ,  Henry Li ,  Stephen Mueller

    IPC: G01R31/08 ,  H04L12/66

    CPC classification number: H04L63/08 ,  H04L47/10 ,  H04L47/2416 ,  H04L47/2433 ,  H04L47/2441 ,  H04L47/6215 ,  H04L49/352 ,  H04L49/355 ,  H04M1/2535 ,  H04M1/6033 ,  H04W88/02

    Abstract: Methods and systems for processing data are disclosed herein and may comprise receiving packetized data via at least one input port in an 802.1p and 802.1Q QoS compliant Ethernet switch integrated within a single gigabit Ethernet IP telephone chip that processes multiple voice channels. A priority class may be assigned by the 802.1p and 802.1Q compliant QoS Ethernet switch to at least a portion of the received packetized data. The received packetized data may be processed by the 802.1p and 802.1Q QoS compliant Ethernet switch based on the assigned priority class. The priority class may comprise a high priority class and/or a low priority class. If the priority class comprises a high priority class, the portion of the received packetized data may be buffered in a high priority buffer integrated within the 802.1p and 802.1Q QoS compliant Ethernet switch.

    Abstract translation: 用于处理数据的方法和系统在本文中公开，并且可以包括经由集成在处理多个语音信道的单个千兆以太网IP电话芯片内的802.1p和802.1Q QoS兼容以太网交换机中的至少一个输入端口接收分组数据。 802.1p和802.1Q兼容的QoS以太网交换机可以将优先级分配给所接收的分组数据的至少一部分。 所接收的分组化数据可以由基于分配的优先级的802.1p和802.1Q QoS兼容以太网交换机来处理。 优先级类可以包括高优先级类和/或低优先级类。 如果优先级类别包括高优先级等级，则接收到的分组化数据的部分可以缓冲在集成在802.1p和802.1Q QoS兼容以太网交换机内的高优先级缓冲器中。

    Method and System for a Gigabit Ethernet IP Telephone Chip with No DSP Core, Which Uses a RISC Core With Instruction Extensions to Support Voice Processing
    39.
    发明申请
    Method and System for a Gigabit Ethernet IP Telephone Chip with No DSP Core, Which Uses a RISC Core With Instruction Extensions to Support Voice Processing 有权
    具有无DSP芯片的千兆以太网IP电话芯片的方法和系统，其使用具有指令扩展的RISC核心来支持语音处理

    公开(公告)号：US20100020791A1

    公开(公告)日：2010-01-28

    申请号：US12555494

    申请日：2009-09-08

    Applicant: Paul Shore ,  Henry Li ,  Balwinder Boora

    Inventor： Paul Shore ,  Henry Li ,  Balwinder Boora

    IPC: H04L12/66

    CPC classification number: H04M1/2535 ,  H04L29/06027 ,  H04L65/604

    Abstract: Methods and systems for processing data are disclosed and may comprise receiving packetized data comprising voice data and network data via an Ethernet switch integrated within a single gigabit Ethernet IP phone chip. The received packetized data may be processed via a single main processor core integrated within the single gigabit Ethernet IP phone chip. The single main processor core may comprise circuitry that is controlled by an instruction set for handling processing of the voice data for a plurality of voice channels without the use of a separate DSP. It may be determined whether data to be processed by the single main processor core is voice data or network data. If the data to be processed by the single main processor core is voice data, at least one modified instruction may be selected from the modified instruction set for processing the voice data.

    Abstract translation: 公开了用于处理数据的方法和系统，并且可以包括通过集成在单个千兆位以太网IP电话芯片内的以太网交换机接收包括语音数据和网络数据的分组数据。 所接收的打包数据可以通过集成在单个千兆以太网IP电话芯片内的单个主处理器核来处理。 单个主处理器核心可以包括由用于处理多个语音信道的语音数据的处理的指令集而不使用单独的DSP来控制的电路。 可以确定要由单个主处理器核心处理的数据是语音数据还是网络数据。 如果要由单个主处理器核心处理的数据是语音数据，则可以从修改的指令集中选择至少一个经修改的指令来处理语音数据。

    Method and system for a gigabit Ethernet IP telephone chip with no DSP core, which uses a RISC core with instruction extensions to support voice processing
    40.
    发明授权
    Method and system for a gigabit Ethernet IP telephone chip with no DSP core, which uses a RISC core with instruction extensions to support voice processing 有权
    用于无DSP芯片的千兆以太网IP电话芯片的方法和系统，其使用具有指令扩展的RISC内核来支持语音处理

    公开(公告)号：US07586904B2

    公开(公告)日：2009-09-08

    申请号：US11151388

    申请日：2005-06-13

    Applicant: Paul Shore ,  Henry Li ,  Balwinder Boora

    Inventor： Paul Shore ,  Henry Li ,  Balwinder Boora

    IPC: H04L12/66 ,  H04J3/16

    CPC classification number: H04M1/2535 ,  H04L29/06027 ,  H04L65/604

    Abstract: Methods and systems for processing data are disclosed and may comprise receiving packetized data comprising voice data and network data via an Ethernet switch integrated within a single gigabit Ethernet IP phone chip. The received packetized data may be processed via a single main processor core integrated within the single gigabit Ethernet IP phone chip. The single main processor core may comprise circuitry that is controlled by an instruction set for handling processing of the voice data for a plurality of voice channels without the use of a separate DSP. It may be determined whether data to be processed by the single main processor core is voice data or network data. If the data to be processed by the single main processor core is voice data, at least one modified instruction may be selected from the modified instruction set for processing the voice data.

    Abstract translation: 公开了用于处理数据的方法和系统，并且可以包括通过集成在单个千兆位以太网IP电话芯片内的以太网交换机接收包括语音数据和网络数据的分组数据。 所接收的打包数据可以通过集成在单个千兆以太网IP电话芯片内的单个主处理器核来处理。 单个主处理器核心可以包括由用于处理多个语音信道的语音数据的处理的指令集而不使用单独的DSP来控制的电路。 可以确定要由单个主处理器核心处理的数据是语音数据还是网络数据。 如果要由单个主处理器核心处理的数据是语音数据，则可以从修改的指令集中选择至少一个经修改的指令来处理语音数据。

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