-
公开(公告)号：US20240213261A1
公开(公告)日：2024-06-27
申请号：US17912121
申请日：2021-06-10
Inventor： Feng WEI , Binyan WANG , Tianyi CHENG , Meng LI
IPC: H01L27/12 , G09G3/3233 , H10K59/121 , H10K59/131
CPC classification number: H01L27/124 , G09G3/3233 , H01L27/1225 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2310/08 , H10K59/1213 , H10K59/131
Abstract: A display panel includes a pixel driving circuit, where the pixel driving circuit includes a driving transistor (T3) and a first transistor (T1), a first electrode of the first transistor (T1) is connected to a gate of the driving transistor (T3), a second electrode thereof is connected to a first initial signal line (Vinit1), the driving transistor (T3) is a P-type low temperature polysilicon transistor, and the first transistor (T1) is an N-type oxide transistor. The display panel further includes: a base substrate, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer.
-
公开(公告)号：US20240203330A1
公开(公告)日：2024-06-20
申请号：US18592002
申请日：2024-02-29
Inventor： Cong LIU , Binyan WANG , Tianyi CHENG , Feng WEI , Meng LI , Shiqian DAI , Kaipeng SUN
IPC: G09G3/32
CPC classification number: G09G3/32 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286
Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. In the display substrate, each signal line includes a first conductive portion; for at least one signal line, the display substrate includes a multi-layer insulating pattern on a side of the first conductive portion away from the base substrate; a first insulating pattern in the multi-layer insulating pattern includes a hollow, and an orthographic projection of the hollow on the base substrate is at least partially in a region surrounded by an orthographic projection of the first conductive portion on the base substrate; and for at least one clock signal line included in the at least one signal line, a ratio between a size of the hollow in a first direction and a size of a shift register unit in the first direction ranges from ¾ to 1.
-
公开(公告)号：US20240112639A1
公开(公告)日：2024-04-04
申请号：US18538715
申请日：2023-12-13
Inventor： Chao ZENG , Weiyun HUANG , Yue LONG , Yao HUANG , Meng LI
IPC: G09G3/3266 , G11C19/28
CPC classification number: G09G3/3266 , G11C19/28 , G09G2300/0426 , G09G2310/0286
Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, a gate driving circuit, power lines, a first signal line group, and a second signal line group. The gate driving circuit includes cascaded shift register units; the power lines are configured to provide power signals to the shift register units; the first signal line group includes at least one clock signal line, and the clock signal line is configured to provide a clock signal to the shift register units; the second signal line group includes a trigger signal line, and the trigger signal line is configured to provide a trigger signal to a first-stage shift register unit; and the gate driving circuit includes at least one transistor, and an extending direction of a channel of the transistor is parallel to an extending direction of the clock signal line.
-
公开(公告)号：US20240078977A1
公开(公告)日：2024-03-07
申请号：US17781870
申请日：2021-07-23
Inventor： Binyan WANG , Cong LIU , Tianyi CHENG , Feng WEI , Meng LI , Shiqian DAI , Kaipeng SUN , Lina WANG
IPC: G09G3/3266
CPC classification number: G09G3/3266 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/08
Abstract: A display substrate and a display apparatus are disclosed. The display substrate includes a base substrate including a display region and a peripheral region located on at least one side of the display region, and a first gate drive circuit, the first gate drive circuit includes a first clock signal line, a second clock signal line and N shift register units that are cascaded; each shift register unit of the N shift register units includes a first output circuit; the first output circuit includes the first output transistor, the orthographic projection of the second clock signal line on the base substrate is located between an orthographic projection of the first output transistor on the base substrate and the orthographic projection of the first clock signal line on the base substrate. The display substrate can reduce load of the first clock signal line and the second clock signal line.
-
公开(公告)号：US20220383820A1
公开(公告)日：2022-12-01
申请号：US16957984
申请日：2019-08-21
Inventor： Chao ZENG , Weiyun HUANG , Yue LONG , Yao HUANG , Meng LI
IPC: G09G3/3266 , G11C19/28
Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, a gate driving circuit, power lines, a first signal line group, and a second signal line group. The gate driving circuit includes cascaded shift register units; the power lines are configured to provide power signals to the shift register units; the first signal line group includes at least one clock signal line, and the clock signal line is configured to provide a clock signal to the shift register units; the second signal line group includes a trigger signal line, and the trigger signal line is configured to provide a trigger signal to a first-stage shift register unit; and the gate driving circuit includes at least one transistor, and an extending direction of a channel of the transistor is parallel to an extending direction of the one clock signal line.
-
Patent Agency Ranking
公开(公告)号：US20220317848A1
公开(公告)日：2022-10-06
申请号：US17298033
申请日：2020-09-07
Inventor： Meng LI , Chao ZENG , Weiyun HUANG
Abstract: A touch panel, preparation method thereof and display apparatus. The touch panel includes a touch region and a binding region, wherein the touch region includes n touch sub-regions disposed sequentially along a second direction, and at least one touch sub-region includes multiple touch electrodes and multiple touch traces; the binding region includes a trace lead-out region adjacent to the touch region, and the trace lead-out region includes n lead convergence regions disposed sequentially along the second direction; first ends of multiple touch traces in an i-th touch sub-region are connected respectively to multiple touch electrodes in the i-th touch sub-region, and second ends of the multiple touch traces in the i-th touch sub-region extend to an i-th lead convergence region of the trace lead-out region; n is a positive integer greater than 2, i=1, 2, . . . , n, and the second direction crosses the first direction.
-
公开(公告)号：US20210407351A1
公开(公告)日：2021-12-30
申请号：US16765317
申请日：2019-07-01
Inventor： Yao HUANG , Weiyun HUANG , Yue LONG , Chao ZENG , Meng LI
Abstract: A display panel and a display drive method thereof, and a display device are provided. The display panel includes a plurality of display regions and a plurality of scan drive circuits, the plurality of display regions includes a first display region and a second display region that are parallel to each other and do not overlap with each other, and the plurality of scan drive circuits includes a first scan drive circuit and a second scan drive circuit, the first and second display regions are connected to the first and second scan drive circuits to respectively receive a first light-emitting control signal, and the display drive method includes: individually adjusting a pulse width of at least one of the first light-emitting control signal and the second light-emitting control signal to adjust the light-emitting durations of light-emitting elements of the first and second display regions within one display period, respectively.
-
公开(公告)号：US20210405410A1
公开(公告)日：2021-12-30
申请号：US17351384
申请日：2021-06-18
Inventor： Chunhua WANG , Rui HAN , Jie YU , Pengtao LI , Tielei ZHAO , Tingfeng HUANG , Meng LI , Shulin QIN , Yaoyao WANG , Xiaoxia WANG , Xiaoqiao DONG
IPC: G02F1/1368 , B60R11/02 , G02F1/1362 , G09G3/34
Abstract: The present disclosure provides a display substrate and a display device, belonging to the field of display technology, which can solve the problem that a splicing gap between existing adjacent display substrates of a spliced screen is relatively wide, and a narrow-bezel display cannot be realized. The display substrate of the present disclosure has a display area and a non-display area surrounding the display area; the display substrate includes a base and a plurality of pixel units located on the base and arranged in the display area; each of the pixel units includes a pixel circuit. The display substrate further includes: a light detection circuit located on the base and arranged in the non-display area; where the light detection circuit is configured to detect brightness of ambient light.
-
公开(公告)号：US20210384288A1
公开(公告)日：2021-12-09
申请号：US17287997
申请日：2020-08-07
Inventor： Meng LI , Yongqian LI , Zhidong YUAN , Can YUAN
IPC: H01L27/32
Abstract: A pixel structure includes: gate lines and data lines disposed crosswise and a plurality of pixel repetition modules distributed in an array. A pixel repetition module includes: a plurality of pixel units arranged in order, wherein each pixel unit includes three sub-pixels arranged in a triangular structure, and the three sub-pixels in each pixel unit and the three sub-pixels in an adjacent pixel unit are arranged inversely with respect to each other; each pixel unit corresponds to two groups of gate lines, wherein each group of gate lines includes two gate lines parallel to each other, a first group of gate lines are located on a first outer side and a second outer side of the pixel units respectively, and a second group of gate lines are both located between the sub-pixels located in a first row and the sub-pixels located in a second row in the pixel units.
-
公开(公告)号：US20210225253A1
公开(公告)日：2021-07-22
申请号：US16312101
申请日：2018-01-04
Inventor： Meng LI , Yongqian LI , Zhidong YUAN , Can YUAN , Zhenfei CAI , Xuehuan FENG
IPC: G09G3/20 , G09G3/3258
Abstract: Embodiments of the present disclosure provide a shift register unit and a driving method thereof, and a gate driving circuit. The shift register unit includes an input circuit, a next-stage start circuit, a control circuit, a stabilization circuit, and at least one output circuit. The at least one output circuit each can control a voltage of a signal output terminal according to a voltage of a pull-up node, a voltage of a pull-down node, a first voltage signal, a control clock signal from a control clock signal terminal, and a control voltage signal from a control voltage signal terminal. A high level of a second clock signal begins when a high level of a first clock signal ends, and a high level of a third clock signal begins when a high level of the second clock signal ends.
-
-
-
-
-
-
-
-
-
Search Results
99
records
(took 0.028 seconds)
