Abstract:
Technologies are generally described for an aggregation of bandwidth from multiple wireless devices. In some examples, a source device may communicate with a destination device at a first bandwidth. The source device may divide data into a first piece and a second piece. The source device may transmit the first piece to a first wireless device and the second piece to a second wireless device over a first network. The first wireless device and second wireless device may communicate with the destination device at a second bandwidth and a third bandwidth respectively. The first bandwidth may be less than an aggregation of the second bandwidth and the third bandwidth. The first wireless device may transmit the first piece over a second network, different from the first network, to the destination device. The second wireless device may transmit the second piece over a third network, different from the first network, to the destination device.
Abstract:
Technologies are generally described for an aggregation of bandwidth from multiple wireless devices. In some examples, a source device may communicate with a destination device at a first bandwidth. The source device may divide data into a first piece and a second piece. The source device may transmit the first piece to a first wireless device and the second piece to a second wireless device over a first network. The first wireless device and second wireless device may communicate with the destination device at a second bandwidth and a third bandwidth respectively. The first bandwidth may be less than an aggregation of the second bandwidth and the third bandwidth. The first wireless device may transmit the first piece over a second network, different from the first network, to the destination device. The second wireless device may transmit the second piece over a third network, different from the first network, to the destination device.
Abstract:
Technologies are generally described for systems, devices and methods effective to monitor performance of a computing device. A computing device may receive a specified counting rate. The computing device may count at the specified counting rate to generate a sequence of counting numbers. The computing device may identify a first output of a process, such as results from computations performed on data, and may identify a first counting number when the first output is identified. The computing device may identify a second output of the process, such as additional results from the computations, and may identify a second counting number when the second output is identified. The computing device may then determine whether an alert should be generated based on the first and second counting numbers such as when a difference between the first and second counting numbers exceeds a threshold value.
Abstract:
Technologies are generally described for systems, devices and methods effective to detect a potential attack on a memory of a memory device. In some examples, a processor may send a request to the memory device. The request may include a request for information that relates to memory writes to the memory of the memory device. The processor may receive a response from the memory device. The response may include the information that relates to the memory writes. The processor may determine, based on the response, an amount of memory of the memory device written to during an interval of time. The processor may detect the potential attack based on the amount of memory written to and based on the interval of time. The processor may then generate an alert based on the detection of the potential attack.
Abstract:
Technologies are generally described for systems, devices and methods effective to utilize a solid state memory device. A memory device may include one or more input/output ports effective to receive data at, and facilitate transfer from, the memory device. The memory device may further include a memory controller. The memory controller may be effective to control access to data stored in the memory device. The memory device may further include two or more flash chips effective to store data in the memory device. The memory device may further include a crossbar switch. The crossbar switch may be coupled between the one or more input/output ports and the two or more flash chips. The crossbar switch may be effective to enable the one or more input/output ports to access the two or more flash chips through the memory controller.
Abstract:
Methods to facilitate monitoring the execution of a first instance and a second instance, such as multiple instantiations of a program, are generally described. The methods may include generating a first instance and a second instance, appending first monitoring instructions to the first instance to produce a first modified instance and appending second monitoring instructions to the second instance to produce a second modified instance. The first and second monitoring instructions may relate to monitoring an execution of the first instance and the second instance. The processor may further send the first modified instance to a first computing device and send the second modified instance to a second computing device different from the first computing device. The computing devices may provide different computational functionality and/or may split a load in processing the program.
Abstract:
Technologies are generally described to establish a hardware interconnect based communication between SSD controllers. According to some examples, a first solid state drive (SSD) controller and a second SSD controller are detected. The hardware interconnect is detected between the first SSD controller and the second SSD controller. Next, a communication connection between the first SSD controller and the second SSD controller is established through the hardware interconnect. The first SSD controller may be allowed to manage a flash controller of the second SSD controller for tasks that include a deduplication task and a low level redundant array of independent disks (RAID) task.