公开(公告)号：US4270026A

公开(公告)日：1981-05-26

申请号：US98105

申请日：1979-11-28

Applicant: Kishan Shenoi ,  Bhagwati P. Agrawal

Inventor： Kishan Shenoi ,  Bhagwati P. Agrawal

IPC: H03M5/04 ,  H03H17/00 ,  H03H17/02 ,  H03H17/04 ,  H03M7/00 ,  H04B14/04 ,  H04Q11/04 ,  G10L1/00

CPC classification number: H04Q11/04 ,  H03H17/0225 ,  H03H17/0416

Abstract: This speech signal digital interpolator increases data (and date rate) by first using an interface unit for rate-changing and zero-stuffing a 32 Kiloword/sec (13 bits/word) signal to form a 1.024 Megaword/sec (13 bits/word) signal, which is then smoothed by a low-pass filter and approximated with 3-bit words. The interface circuit repeats each word a given number of times at the increased rate with each word separated by an all zero bit word having the same number of bits as the digital word to provide an output signal of a specified pattern for each word in the digital signal. A low pass recursive filter responds to the output signal from the interface means and is operative to provide a filtered output digital signal having smooth transitions between each output digital word with said filter output signal at said increased rate and with each output filtered digital word being of a lesser number of bits than the bits in said original signal. Due to the selection of the filter configuration, the coefficients of the filter are restricted to be of the form 2.sup.-K to thereby implement the recursive filter without the use of digital multipliers.

Abstract translation: 该语音信号数字内插器通过首先使用接口单元来增加数据（和日期速率），用于速率改变和填充32个千瓦/秒（13比特/字）信号以形成1.024兆字/秒（13比特/字 ）信号，然后由低通滤波器平滑，并用3位字近似。 接口电路以增加的速率重复给定次数的每个字，每个字由与数字字相同数量的位的全零位字分隔，以提供数字中的每个字的指定模式的输出信号 信号。 低通递归滤波器响应于来自接口装置的输出信号，并且可操作地提供滤波后的输出数字信号，该数字信号在每个输出数字字与所述滤波器输出信号之间以所述增加的速率具有平滑的转换，并且每个输出滤波的数字字为 比所述原始信号中的比特少的比特数。 由于滤波器配置的选择，滤波器的系数被限制为2-K形式，从而在不使用数字乘法器的情况下实现递归滤波器。

公开(公告)号：US08274999B2

公开(公告)日：2012-09-25

申请号：US12830268

申请日：2010-07-02

Applicant: Kishan Shenoi ,  George P. Zampetti ,  Lee Cosart

Inventor： Kishan Shenoi ,  George P. Zampetti ,  Lee Cosart

IPC: H04J3/06

CPC classification number: H04J3/0641 ,  H04J3/0682 ,  H04L41/082 ,  H04L45/00 ,  H04L45/121

Abstract: Packet network performance is assessed using transit delay metrics and compliance masks generated at various evaluation nodes of the network. The evaluation nodes may employ network probes that make precise measurements of transit delays and thereby of transit delay variations. Based on the assessments, a master may be added to the network or relocated within the network, rate of timing packets generated by the master may be adjusted up or down, or oscillators used at the slaves may be upgraded.

Abstract translation: 使用在网络的各种评估节点处生成的传输延迟度量和合规性掩码来评估分组网络性能。 评估节点可以使用网络探针，其对传输延迟进行精确测量，从而进行传输延迟变化。 基于评估，可以将主机添加到网络中或重新定位在网络内，由主机产生的定时分组的速率可以被上调或下调，或者可以升级从站使用的振荡器。

公开(公告)号：US20110235500A1

公开(公告)日：2011-09-29

申请号：US13065584

申请日：2011-03-24

Applicant: Kishan Shenoi

Inventor： Kishan Shenoi

IPC: H04J3/10

CPC classification number: H04J3/0632 ,  H04L7/005

Abstract: A method includes operating an integrated echo canceller and speech codec for voice-over internet protocol. An apparatus includes an echo canceller and a speech codec, wherein the speech codec includes a decoder and an encoder, and wherein the echo canceller and the speech codec are integrated for voice-over-internet protocol.

Abstract translation: 一种方法包括操作集成的回声消除器和语音编解码器，用于语音互联网协议。 一种装置包括回声消除器和语音编解码器，其中语音编解码器包括解码器和编码器，并且其中回声消除器和语音编解码器被集成用于互联网语音协议。

公开(公告)号：US20110234200A1

公开(公告)日：2011-09-29

申请号：US13065583

申请日：2011-03-24

Applicant: Kishan Shenoi

Inventor： Kishan Shenoi

IPC: G01R13/34

CPC classification number: H04J3/0632 ,  H04L7/005

Abstract: A method includes monitoring a fill in an adaptive slip buffer of a digital to analog convertor; adjusting a number of samples that are read from the adaptive slip buffer per page as a function of the fill; and reading the number of samples from the adaptive slip buffer. An apparatus includes a digital to analog convertor including an adaptive slip buffer and a read address generator coupled to the adaptive slip buffer, wherein the read address generator includes an increment control that adjusts a number of samples that are read from the adaptive slip buffer per page as a function of fill of the adaptive slip buffer.

Abstract translation: 一种方法包括监视数字到模拟转换器的自适应滑动缓冲器中的填充; 调整从每页自适应滑动缓冲器中读取的样本数量作为填充的函数; 并从自适应滑动缓冲器读取样本数。 一种装置包括数模转换器，其包括耦合到自适应滑动缓冲器的自适应滑移缓冲器和读地址发生器，其中读地址生成器包括增量控制器，其调整从每页自适应滑动缓冲器读取的采样数量 作为自适应滑动缓冲器的填充的函数。

公开(公告)号：US07636022B2

公开(公告)日：2009-12-22

申请号：US11451652

申请日：2006-06-12

Applicant: Kishan Shenoi

Inventor： Kishan Shenoi

IPC: H03B1/00

CPC classification number: H04J3/0632

Abstract: Methods and apparatus are described for a play-out buffer. A method includes writing a data packet into a jitter buffer at a write address specified by a write address generator; incrementing the write address generator; generating the difference between the write address and a current read address specified by a read address generator; reading a data packet from the jitter buffer from the current read address specified by the read address generator; generating a new read address based on the difference between the write address and the current read address by the read address generator. An apparatus includes a jitter buffer; a write address generator for storing a write address; a read address generator for storing a current read address; a read address increment control; wherein the read address increment control sets the future read address based on the difference between the write address and the current read address. Another method of driving a numerically controlled oscillator includes providing a local clock with a clock cycle; generating a numerical value during each clock cycle; adding the numerical value to an accumulator having a most significant bit; and using the value of the most significant bit as an oscillator. Another apparatus includes a local clock with a clock cycle; a jitter buffer having a write address and a current read address; a first accumulator; a second accumulator having a most significant bit; an increment control; wherein the increment control sets an accumulation value to be added to the first accumulator based on the difference between the write address and the current read address; wherein the value of the second accumulator depends on the first accumulator; and wherein the most significant bit functions as an oscillator.

Abstract translation: 对于播放缓冲器描述了方法和装置。 一种方法包括以写地址发生器指定的写地址将数据包写入抖动缓冲器; 增加写地址生成器; 产生写地址和由读地址生成器指定的当前读地址之间的差; 从读取地址生成器指定的当前读取地址读取来自抖动缓冲器的数据包; 基于读取地址生成器的写入地址和当前读取地址之间的差异生成新的读取地址。 一种装置包括抖动缓冲器; 用于存储写入地址的写入地址生成器; 用于存储当前读取地址的读取地址发生器; 读地址增量控制; 其中读地址增量控制器基于写地址和当前读地址之间的差设置未来读地址。 驱动数控振荡器的另一种方法包括：提供具有时钟周期的本地时钟; 在每个时钟周期内产生数值; 将数值加到具有最高有效位的累加器; 并使用最高有效位的值作为振荡器。 另一种装置包括具有时钟周期的本地时钟; 具有写入地址和当前读取地址的抖动缓冲器; 第一个蓄电池; 具有最高有效位的第二累加器; 增量控制 其中所述增量控制器基于所述写入地址和所述当前读取地址之间的差异来设置要添加到所述第一累加器的累加值; 其中所述第二累加器的值取决于所述第一累加器; 并且其中最高有效位用作振荡器。

公开(公告)号：US20070036180A1

公开(公告)日：2007-02-15

申请号：US11451652

申请日：2006-06-12

Applicant: Kishan Shenoi

Inventor： Kishan Shenoi

IPC: H04J3/06

CPC classification number: H04J3/0632

Abstract: Methods and apparatus are described for a play-out buffer. A method includes writing a data packet into a jitter buffer at a write address specified by a write address generator; incrementing the write address generator; generating the difference between the write address and a current read address specified by a read address generator; reading a data packet from the jitter buffer from the current read address specified by the read address generator; generating a new read address based on the difference between the write address and the current read address by the read address generator. An apparatus includes a jitter buffer; a write address generator for storing a write address; a read address generator for storing a current read address; a read address increment control; wherein the read address increment control sets the future read address based on the difference between the write address and the current read address. Another method of driving a numerically controlled oscillator includes providing a local clock with a clock cycle; generating a numerical value during each clock cycle; adding the numerical value to an accumulator having a most significant bit; and using the value of the most significant bit as an oscillator. Another apparatus includes a local clock with a clock cycle; a jitter buffer having a write address and a current read address; a first accumulator; a second accumulator having a most significant bit; an increment control; wherein the increment control sets an accumulation value to be added to the first accumulator based on the difference between the write address and the current read address; wherein the value of the second accumulator depends on the first accumulator; and wherein the most significant bit functions as an oscillator.

Abstract translation: 对于播放缓冲器描述了方法和装置。 一种方法包括以写地址发生器指定的写地址将数据包写入抖动缓冲器; 增加写地址生成器; 产生写地址和由读地址生成器指定的当前读地址之间的差; 从读取地址生成器指定的当前读取地址读取来自抖动缓冲器的数据包; 基于读取地址生成器的写入地址和当前读取地址之间的差异生成新的读取地址。 一种装置包括抖动缓冲器; 用于存储写入地址的写入地址生成器; 用于存储当前读取地址的读取地址发生器; 读地址增量控制; 其中读地址增量控制器基于写地址和当前读地址之间的差设置未来读地址。 驱动数控振荡器的另一种方法包括：提供具有时钟周期的本地时钟; 在每个时钟周期内产生数值; 将数值加到具有最高有效位的累加器; 并使用最高有效位的值作为振荡器。 另一种装置包括具有时钟周期的本地时钟; 具有写入地址和当前读取地址的抖动缓冲器; 第一个蓄电池; 具有最高有效位的第二累加器; 增量控制 其中所述增量控制器基于所述写入地址和所述当前读取地址之间的差异来设置要添加到所述第一累加器的累加值; 其中所述第二累加器的值取决于所述第一累加器; 并且其中最高有效位用作振荡器。

公开(公告)号：US07158523B2

公开(公告)日：2007-01-02

申请号：US10145247

申请日：2002-05-14

Applicant: Gary Jacobson ,  Kamila Kraba ,  Chien-Chou Lai ,  Jeremy Sommer ,  Jining Yang ,  Kishan Shenoi

Inventor： Gary Jacobson ,  Kamila Kraba ,  Chien-Chou Lai ,  Jeremy Sommer ,  Jining Yang ,  Kishan Shenoi

IPC: H04L12/00

CPC classification number: H04L12/5601 ,  H04L2012/5652 ,  H04L2012/5672

Abstract: Systems and methods are described for bonding asynchronous transfer mode permanent virtual circuits using a multi-link segmentation and reassembly sublayer. A method includes: transforming a stream of asynchronous transfer mode cells into a stream of bonded asynchronous transfer mode cells; demultiplexing the stream of bonded asynchronous transfer mode cells into a plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells; and transmitting the plurality of streams of inverse multiplexed bonded asynchronous transfer mode cells to a remote location via a plurality of permanent virtual circuits, characterized in that the transmitted plurality of streams of inverse multiplexed bonded asynchronized transfer mode cells can be multiplexed into a multiplexed stream of asynchronized transfer mode cells after transmission via at least two permanent virtual circuits, which compose the plurality of permanent virtual circuits, that do not have an identical bit-rate.

Abstract translation: 描述了使用多链路分段和重组子层来绑定异步传输模式永久虚拟电路的系统和方法。 一种方法包括：将异步传输模式信元流转换成绑定异步传输模式信元流; 将接合的异步传输模式小区的流解复用为多个反向复用的并联异步传输模式小区的多个流; 并且经由多个永久虚拟电路将多个逆向多路复用的接合异步传输模式小区的多个流发送到远程位置，其特征在于，所发送的多个反向多路复用的非同步传输模式小区的多个流可以被多路复用为 通过构成多个永久虚拟电路的至少两个永久虚拟电路在不具有相同比特率的传输之后的非同步传输模式信元。

公开(公告)号：US07142619B2

公开(公告)日：2006-11-28

申请号：US09843161

申请日：2001-04-25

Applicant: Jeremy Sommer ,  Kishan Shenoi ,  Kamila Kraba ,  Sandro Squadrito ,  Gary Bogardus

Inventor： Jeremy Sommer ,  Kishan Shenoi ,  Kamila Kraba ,  Sandro Squadrito ,  Gary Bogardus

IPC: H04L27/08

CPC classification number: H04B3/06 ,  H04L25/24

Abstract: Systems and methods are described for long subscriber loops using automatic gain control. A method includes extending a digital subscriber loop including: producing an output signal in a first direction from a variable gain amplifier at a mid-span extender unit responsive to an input signal in the first direction from the digital subscriber loop; monitoring a signal strength of said output signal in the first direction at the mid-span extender unit; generating a gain control signal responsive to the signal strength at the mid-span extender unit; controlling a gain of the variable gain amplifier at the mid-span extender unit responsive to the gain control signal; and controlling a second gain of a second variable gain amplifier at said mid-span extender unit responsive to said gain control signal to produce an output signal in a second direction from said second variable gain amplifier at said mid-span extender unit responsive to a second input signal in said second direction from said digital subscriber loop.

Abstract translation: 对使用自动增益控制的长用户回路描述系统和方法。 一种方法包括扩展数字用户环路，包括：响应于来自数字用户环路的第一方向上的输入信号，在中跨扩展器单元处从可变增益放大器产生在第一方向上的输出信号; 在中跨扩展器单元处监测所述输出信号在第一方向上的信号强度; 响应于中跨扩展器单元处的信号强度产生增益控制信号; 响应于增益控制信号控制中跨扩展器单元处的可变增益放大器的增益; 以及响应于所述增益控制信号，在所述中跨延伸器单元处控制第二可变增益放大器的第二增益，以在所述中跨扩展器单元处产生来自所述第二可变增益放大器的第二方向的输出信号， 从所述数字用户回路在所述第二方向输入信号。

公开(公告)号：US06549604B2

公开(公告)日：2003-04-15

申请号：US09749249

申请日：2000-12-26

Applicant: Kishan Shenoi

Inventor： Kishan Shenoi

IPC: H03K2100

CPC classification number: H03L7/089 ,  H03L7/0992 ,  H03L7/0994 ,  H04L7/033 ,  H04L7/0331

Abstract: Systems and methods are described for clock recovery and detection of rapid phase transients. An apparatus includes: a numerically controlled oscillator; a phase detector coupled to the numerically controlled oscillator; and a multiplexer coupled to the phase detector and the numerically controlled oscillator, wherein a) the phase detector sets a state variable indicator to either i) a high value if an output phase of the numerically controlled oscillator lags an incoming signal phase, or ii) a low value if the output phase leads the incoming signal phase, b) the multiplexer sends either i) a high increment to the numerically controlled oscillator if the state variable indicator has been set to the high value, or ii) a low increment to the numerically controlled oscillator if the state variable indicator has been set to the low value, and c) the numerically controlled oscillator either i) advances the output phase if the high increment has been sent to the numerically controlled oscillator, or ii) retards the output phase if the low increment has been sent to the numerically controlled oscillator. A method includes incrementing a high counter once every clock cycle if a state variable indicator is high; clearing a low counter if the state variable indicator is high; incrementing the low counter once every clock cycle if the state variable indicator is low; clearing the high counter if the state variable indicator is low; and triggering an alarm signal if either i) the low counter exceeds a low count threshold or ii) the high counter exceeds a high count threshold.

公开(公告)号：US5280532A

公开(公告)日：1994-01-18

申请号：US506452

申请日：1990-04-09

Applicant: Kishan Shenoi ,  Patrick L. Hanagan ,  Helena S. Ho ,  Frank I. Yu

Inventor： Kishan Shenoi ,  Patrick L. Hanagan ,  Helena S. Ho ,  Frank I. Yu

IPC: H04J3/00 ,  H04J3/17 ,  G10L7/08

CPC classification number: G10L19/00 ,  H04J3/172

Abstract: An N:1 data compression system for compressing data on N DS1 trunks carrying 4N channels is disclosed. Waveform encoding circuitry is coupled to the N DS1 trunks for compressing the DS1 data into x bits and producing both encoded data and control parameters, where x.ltoreq.8. The system further includes circuitry coupled to the waveform encoding circuitry for receiving the encoded data and control parameters, performing digital speech interpolation and producing data packets which may include encoded data and control parameters that are transmittable on a single DS1 trunk.

Abstract translation: 公开了一种用于压缩携带4N信道的N个DS1中继上的数据的N：1数据压缩系统。 波形编码电路耦合到N DS1中继线，用于将DS1数据压缩为x位，并产生编码数据和控制参数，其中x <= 8。 该系统还包括耦合到波形编码电路的电路，用于接收编码数据和控制参数，执行数字语音内插并产生可包括可在单个DS1中继线上传送的编码数据和控制参数的数据分组。