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    BATTERY CHARGING CUT-OFF CIRCUIT
    31.
    发明申请
    BATTERY CHARGING CUT-OFF CIRCUIT 审中-公开

    公开(公告)号：US20190222035A1

    公开(公告)日：2019-07-18

    申请号：US15871999

    申请日：2018-01-16

    Applicant: Cisco Technology, Inc.

    Inventor： Xiqun Zhu ,  Sung Kee Baek ,  Wingo Cheong ,  Steven Anthony Granzella ,  Joel Goergen ,  Charles Calvin Byers

    IPC: H02J7/00

    CPC classification number: H02J7/0021

    Abstract: In one embodiment, a battery backup unit (BBU) cut-off and recharge circuit includes: a first transistor, a power entry connection connected to a main power supply, where power from the power entry connection flows to application circuits for an electronic device, and the first transistor is positioned between a BBU and the power entry connection, and a microcontroller, where the microcontroller is operative to: detect a loss of power from the main power supply, turn on the first transistor to enable the BBU to discharge through the power entry connection to application circuits, detect a status of charge (SOC) for the BBU, and upon detecting that the SOC is under a predefined threshold, set the BBU cut-off and recharge circuit to a lockdown state by turning off the first transistor.

    METHOD AND SYSTEM TO PREVENT VOLTAGE SAGGING IN A REDUNDANT POWER SUPPLY CONFIGURATION
    32.
    发明申请
    METHOD AND SYSTEM TO PREVENT VOLTAGE SAGGING IN A REDUNDANT POWER SUPPLY CONFIGURATION 有权

    公开(公告)号：US20170163027A1

    公开(公告)日：2017-06-08

    申请号：US15439725

    申请日：2017-02-22

    Applicant: CISCO TECHNOLOGY, INC.

    Inventor： Weizhong Tang ,  Sung Kee Baek ,  Craig Zimmerman

    IPC: H02H7/12 ,  H03K17/082

    CPC classification number: H02H7/1213 ,  G06F1/26 ,  G06F11/16 ,  G06F11/2015 ,  H03K17/0822 ,  H04M19/08

    Abstract: Aspects of the subject technology relate to a system and method for preventing voltage sagging using an Oring-FET in a redundant power supply configuration. Each redundant power supply includes an Oring-FET and a voltage comparator. The voltage comparator receives and compares an input voltage and an output voltage of the Oring-FET during power up. In the event input voltage is less than the output voltage, the Oring-FET is deemed to be operating properly and provides output to a communicatively coupled system bus in response to the input voltage reaching a predetermined voltage threshold level. In the event the input voltage is approximately equal to the output voltage, the voltage comparator assists in preventing inrush current from flowing from the communicatively coupled system bus and prevents voltage sagging on the communicatively coupled system bus when another redundant power supply configuration is providing power to the communicatively coupled system bus.

    METHOD AND SYSTEM TO PREVENT BUS VOLTAGE SAGGING WHEN AN ORING-FET IN AN N+1 REDUNDANT POWER SUPPLY CONFIGURATION IS FAULTY DURING POWER UP
    33.
    发明申请
    METHOD AND SYSTEM TO PREVENT BUS VOLTAGE SAGGING WHEN AN ORING-FET IN AN N+1 REDUNDANT POWER SUPPLY CONFIGURATION IS FAULTY DURING POWER UP 有权
    当N + 1冗余电源配置中的OR-FET在上电期间发生故障时，可以防止总线电压发生的方法和系统

    公开(公告)号：US20150270700A1

    公开(公告)日：2015-09-24

    申请号：US14220905

    申请日：2014-03-20

    Applicant: Cisco Technology, Inc.

    Inventor： Weizhong Tang ,  Sung Kee Baek ,  Craig Zimmerman

    IPC: H02H7/12

    CPC classification number: H02H7/1213 ,  G06F1/26 ,  G06F11/16 ,  G06F11/2015 ,  H03K17/0822 ,  H04M19/08

    Abstract: A system and method for preventing bus voltage sagging when an Oring-FET in an N+1 redundant power supply configuration is faulty during power up. Each redundant power supply includes an Oring-FET and a voltage comparator. The voltage comparator receives and compares an input voltage and an output voltage of the Oring-FET during power up. In the event input voltage is less than the output voltage, the Oring-FET is deemed to be operating properly and provides output to a communicatively coupled system bus in response to the input voltage reaching a predetermined voltage threshold level. In the event the input voltage is approximately equal to the output voltage, the voltage comparator assists in preventing inrush current from flowing from the communicatively coupled system bus and prevents voltage sagging on the communicatively coupled system bus when another redundant power supply configuration is providing power to the communicatively coupled system bus.

    Abstract translation: 当在N + 1冗余电源配置中的Oring-FET在上电期间发生故障时，用于防止总线电压下垂的系统和方法。 每个冗余电源包括Oring-FET和电压比较器。 电压比较器在上电期间接收和比较Oring-FET的输入电压和输出电压。 在输入电压小于输出电压的情况下，Oring-FET被认为正常工作，并且响应于输入电压达到预定的电压阈值电平，向通信耦合的系统总线提供输出。 在输入电压近似等于输出电压的情况下，电压比较器有助于防止浪涌电流从通信耦合的系统总线流出，并且当另一冗余电源配置提供电力时防止在通信耦合的系统总线上的电压下垂 通信耦合系统总线。

    Battery charging cut-off circuit
    36.
    发明授权
    Battery charging cut-off circuit 有权

    公开(公告)号：US11909255B2

    公开(公告)日：2024-02-20

    申请号：US17702944

    申请日：2022-03-24

    Applicant: Cisco Technology, Inc.

    Inventor： Xiqun Zhu ,  Sung Kee Baek ,  Wingo Cheong ,  Steven Anthony Granzella ,  Joel Goergen ,  Charles Calvin Byers

    IPC: H02J9/06 ,  H02J7/00

    CPC classification number: H02J9/061 ,  H02J7/00309 ,  H02J7/00306

    Abstract: In one embodiment, a battery backup unit (BBU) cut-off and recharge circuit includes: a first transistor, a power entry connection connected to a main power supply, where power from the power entry connection flows to application circuits for an electronic device, and the first transistor is positioned between a BBU and the power entry connection, and a microcontroller, where the microcontroller is operative to: detect a loss of power from the main power supply, turn on the first transistor to enable the BBU to discharge through the power entry connection to application circuits, detect a status of charge (SOC) for the BBU, and upon detecting that the SOC is under a predefined threshold, set the BBU cut-off and recharge circuit to a lockdown state by turning off the first transistor.

    MODULAR POWER SUPPLY ARCHITECTURE OPTIMIZED FOR FLAT EFFICIENCY ACROSS LOADINGS
    37.
    发明公开
    MODULAR POWER SUPPLY ARCHITECTURE OPTIMIZED FOR FLAT EFFICIENCY ACROSS LOADINGS 审中-公开

    公开(公告)号：US20230361668A1

    公开(公告)日：2023-11-09

    申请号：US18353536

    申请日：2023-07-17

    Applicant: Cisco Technology, Inc.

    Inventor： Xiqun Zhu ,  Sung Kee Baek ,  Joel Goergen ,  Doug Paul Arduini ,  Ruqi Li

    IPC: H02M1/00

    CPC classification number: H02M1/0048 ,  H02M1/0043

    Abstract: A control method improves the efficiency profile of a power supply across a wide range of output loading. The method includes obtaining a measure of output power for a power supply, which includes one or more output modules and an auxiliary power supply. The method determines whether a maximum power rating of the auxiliary power supply is sufficient to provide the measure of output power. Responsive to a determination that the maximum power rating of the auxiliary power supply is sufficient to provide the measure of output power, the controller of the power supply directs the auxiliary power supply to provide the output power.

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