公开(公告)号：US09898959B2

公开(公告)日：2018-02-20

申请号：US14914576

申请日：2015-08-21

Applicant: BOE Technology Group Co., Ltd.

Inventor： Quanhu Li

IPC: G11C19/00 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/36 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G11C19/28

Abstract: A control sub-unit, a shift register unit, a shift register, a gate driving circuit and a display apparatus. The control sub-unit comprises a low level input terminal (VGL), a selection module and N sets of nodes (Q1′, QB1′, Q2′, QB2′ . . . QN′, QBN′), each set of nodes (Q1′, QB1′, Q2′, QB2′ . . . QN′, QBN′) comprises a first control node (Q1′, Q2′, . . . QN′) and a second control node (QB1′, QB2′ . . . QBN′), when the first control node (Q1′) in one set of nodes (Q1′, QB1′) among the N sets of nodes is at a high level and the second control node (QB1′) in said one set of nodes (Q1′, QB1′) is at a low level, the selection module connects the second control nodes (QB2′ . . . QBN′) of the other N−1 sets of nodes (Q2′, QB2′ . . . QN′, QBN′) to the low level input terminal, such that the first control nodes (Q2′, . . . QN′) and the second control nodes (QB2′ . . . QBN′) in the other N−1 sets of nodes (Q2′, QB2′ . . . QN′, QBN′) are all at the low level, wherein N is a positive integer larger than 1.

公开(公告)号：US09818339B2

公开(公告)日：2017-11-14

申请号：US14906369

申请日：2015-08-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Quanhu Li

IPC: G11C19/00 ,  G09G3/3225 ,  G09G3/3266 ,  G11C19/28 ,  G09G3/36

CPC classification number: G09G3/3225 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G11C19/28

Abstract: A shift register unit, a method for driving the same and a gate scanning circuit are provided. The shift register unit comprises an input module for receiving a signal to be shifted, an output module, a reset module and a reset control module, an output terminal of the input module, a control terminal of the output module and an output terminal of the reset module are connected to a first node, an output terminal of the reset control module is connected with a control terminal of the reset module for turning on the reset module under control of control signal received by control terminal of the reset control module to reset the first node, the output module outputs a shifted signal with multiple pulses before the first node is reset. According to the present invention, a gate driving signal with multiple pulses can be outputted by one shift register unit.

公开(公告)号：US09799270B2

公开(公告)日：2017-10-24

申请号：US15226702

申请日：2016-08-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yongqian Li ,  Yicheng Lin ,  Quanhu Li

IPC: G09G3/3258

CPC classification number: G09G3/3258 ,  G09G3/20 ,  G09G2300/0426 ,  G09G2310/08

Abstract: Disclosed is a pixel circuit which includes a multiplexing module and a plurality of sub-pixels. Signals for detecting parameters of respective sub-pixels are transferred via a sensing line in a time-divisional manner. For each sub-pixel, connection to the data line and the sensing line is achieved via a common terminal. Further disclosed are a display panel and a display device.

公开(公告)号：US20170040351A1

公开(公告)日：2017-02-09

申请号：US14913322

申请日：2015-08-13

Applicant: Boe Technology Group Co., Ltd.

Inventor： Quanhu Li ,  Yongqian Li ,  Longyan Wang

IPC: H01L27/12 ,  H01L21/768

CPC classification number: H01L27/1259 ,  H01L21/76805 ,  H01L21/76892 ,  H01L21/77 ,  H01L27/0288 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248

Abstract: The embodiments of the present disclosure provide an array substrate and manufacturing method thereof, and a display device, which relates to the display technical field. The manufacturing method of the array substrate comprises forming thin film transistors and signal lines, and further comprises forming signal line connecting lines, wherein the signal line connecting lines at least electrically connect the same type of signal lines. Prior to completion of manufacturing the last film layer in the manufacture procedure of said array substrate, the method further comprises etching via holes on the signal line connecting lines or at the positions of the signal lines which are close to the signal line connecting lines, said via holes being used for cutting off electric connections between the signal lines. It is for use in the manufacture of an array substrate and display device.

Abstract translation: 本公开的实施例提供阵列基板及其制造方法以及与显示技术领域有关的显示装置。 阵列基板的制造方法包括形成薄膜晶体管和信号线，并且还包括形成信号线连接线，其中信号线连接线至少电连接相同类型的信号线。 在制造所述阵列基板的制造过程中的最后一个薄膜层之前，该方法还包括在信号线连接线上或靠近信号线连接线的信号线的位置处蚀刻通孔，所述 通孔用于切断信号线之间的电连接。 它用于制造阵列基板和显示装置。

公开(公告)号：US20170025057A1

公开(公告)日：2017-01-26

申请号：US15097534

申请日：2016-04-13

Applicant: BOE Technology Group Co., Ltd.

Inventor： Quanhu Li

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/3266 ,  G09G2310/0286 ,  G11C19/287

Abstract: The present disclosure relates to display technology, and provides an inverter, a gate driving circuit and a display apparatus, capable of solving the problem that it is difficult to apply Scan Power technology in the display apparatus since a power signal outputted from the inverter has a small current. The inverter comprises: a current amplification module configured to amplify a current of the output terminal of the inverter based on a signal at a first clock signal terminal, a signal at a second clock signal terminal, a signal at a third clock signal terminal, a signal at a fourth clock signal terminal, a signal at a first input signal terminal, and a signal at a second input signal terminal, and to control the output terminal of the inverter to output a high level signal; and a pull-down module configured to control the output terminal of the inverter to output a low level signal. The inverter according to the present disclosure may be applied in a display apparatus employing the Scan Power technology.

Abstract translation: 本公开涉及显示技术，并且提供了一种逆变器，栅极驱动电路和显示装置，其能够解决难以将扫描电力技术应用于显示装置的问题，因为从逆变器输出的电力信号具有 小电流 逆变器包括：电流放大模块，被配置为基于第一时钟信号端子处的信号，第二时钟信号端子处的信号，第三时钟信号端子处的信号，放大反相器的输出端子的电流， 在第四时钟信号端子处的信号，第一输入信号端子处的信号和第二输入信号端子处的信号，并且控制反相器的输出端子输出高电平信号; 以及配置成控制所述逆变器的输出端子以输出低电平信号的下拉模块。 根据本公开的逆变器可以应用于采用扫描电力技术的显示装置中。

公开(公告)号：US09536469B2

公开(公告)日：2017-01-03

申请号：US14769068

申请日：2015-01-06

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Quanhu Li ,  Chen Song

IPC: G09G3/3225 ,  G09G3/32

CPC classification number: G09G3/3225 ,  G09G3/3266 ,  G09G2300/0809 ,  G09G2310/0213 ,  G09G2310/0218

Abstract: Disclosed is a pulse signal combination circuit for combining N input pulse signals sequentially effective within each display period into an output pulse signal, N being an integer greater than 1, including N output control units and a pulse signal output end. A first control end of an nth output control unit is configured to receive an nth input pulse signal, a second control end thereof is configured to receive an (n+1)th input pulse signal, and an output end thereof is connected to the pulse signal output end. The nth output control unit is configured to, within a time duration of each display period after the nth input pulse signal is effective for the first time and before the (n+1)th input pulse signal is effective for the first time, output the nth input pulse signal to the pulse signal output end, where n is a positive integer less than N.

Abstract translation: 公开了一种脉冲信号组合电路，用于将在每个显示周期内顺序有效的N个输入脉冲信号组合成输出脉冲信号，N是大于1的整数，包括N个输出控制单元和脉冲信号输出端。 第n输出控制单元的第一控制端被配置为接收第n输入脉冲信号，其第二控制端被配置为接收第（n + 1）个输入脉冲信号，并且其输出端连接到脉冲 信号输出端。 第n输出控制单元被配置为在第n个输入脉冲信号在第一次有效之后且在第（n + 1）个输入脉冲信号第一次有效之前的每个显示周期的持续时间内，输出 第n个输入脉冲信号到脉冲信号输出端，其中n是小于N的正整数。

公开(公告)号：US11342037B2

公开(公告)日：2022-05-24

申请号：US16609723

申请日：2019-03-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Quanhu Li

IPC: G09G3/3266 ,  G11C19/28 ,  G09G3/36

Abstract: The present disclosure provides a shift register unit, a driving method, a light emitting control gate driving circuit, and a display apparatus. The shift register unit includes: a light emitting control signal output terminal, a pull-up control node control circuit, N stages of inversion control circuits, a pull-up node control circuit, a pull-down node control circuit, and an output circuit, where N is an integer greater than 1. A first stage of inversion control circuit is configured to invert an input signal. An nth stage of inversion control circuit inverts the input signal under control of an (n−1)th inversion node, where n is an integer and 2≤n≤N.

公开(公告)号：US20210335255A1

公开(公告)日：2021-10-28

申请号：US16609723

申请日：2019-03-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Quanhu Li

IPC: G09G3/3258 ,  G09G3/3266 ,  G11C19/28

Abstract: The present disclosure provides a shift register unit, a driving method, a light emitting control gate driving circuit, and a display apparatus. The shift register unit includes: a light emitting control signal output terminal, a pull-up control node control circuit, N stages of inversion control circuits, a pull-up node control circuit, a pull-down node control circuit, and an output circuit, where N is an integer greater than 1. A first stage of inversion control circuit is configured to invert an input signal. An nth stage of inversion control circuit inverts the input signal under control of an (n−1)th inversion node, where n is an integer and 2≤n≤N.

公开(公告)号：US11120720B2

公开(公告)日：2021-09-14

申请号：US16649720

申请日：2019-05-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Quanhu Li

IPC: G09G3/3266 ,  G09G3/36 ,  G11C19/28 ,  G09G3/20

Abstract: A shift register unit and a method for driving the same, a gate driver including the same, a display panel and a display device. The shift register unit includes an input terminal, a first voltage terminal, a second voltage terminal, a first clock signal terminal, a second clock signal terminal, an adjustment terminal, an output terminal, a transfer terminal, an input circuit, a first control circuit, and an output circuit. The shift register unit avoids unstableness of the output signal caused by abnormal leakage of charges during the normal output by providing an adjustment signal, and separates the output signal from the transfer signal by means of the output terminal and the transfer terminal, which can reduce the sizes of transistors connected to the output terminal and the transfer terminal, thereby saving the layout area of the shift register unit and decreasing the power consumption thereof at the same time.

公开(公告)号：US20210201790A1

公开(公告)日：2021-07-01

申请号：US16071667

申请日：2017-08-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Cuili Gai ,  Zhongyuan Wu ,  Baoxia Zhang ,  Ling Wang ,  Yicheng Lin ,  Quanhu Li ,  Fang Liu

IPC: G09G3/3258 ,  G09G3/3233 ,  G09G3/3291

Abstract: The present application discloses a pixel circuit in an active matrix organic light-emitting diode (AMOLED) display panel. The pixel circuit includes a first transistor having a bottom gate and a top gate, a drain supplied with a high-level power-supply voltage, and a source coupled to a light-emitting diode (LED). The bottom gate is provided with a first voltage signal and the source is provided with a second voltage signal in a compensation period during which a present value of a threshold voltage of the first transistor is sensed at the source and a third voltage signal is determined based on the present value of the threshold voltage. The top gate is configured to be provided with the third voltage signal in an emission period to reduce the present value of the threshold voltage.