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公开(公告)号：US10885821B2
公开(公告)日：2021-01-05
申请号：US16399859
申请日：2019-04-30
Inventor： Guangyao Li , Bo Mao , Xuehai Gui , Qinghe Wang , Jun Wang , Dongfang Wang , Liangchen Yan
IPC: G09G3/00 , G09G3/3225 , H01L27/32 , H01L51/00 , H01L51/52
Abstract: An inspection device includes: a driving circuit, configured to input display data of an image to a pixel electrode of the array substrate; a light-emitting device comprising a first electrode, a second electrode, and a plurality of light-emitting units arranged between the first electrode and the second electrode, and the plurality of light-emitting units is capable of emitting light under the effect of an electric field between the first electrode and the second electrode; a test circuit, configured to electrically connect the first electrode of the light-emitting device to the pixel electrode of the array substrate, and input a first electrical signal to the second electrode of the light-emitting device, to generate the electric field; and a processing circuit, configured to acquire optical information of the light emitted by the light-emitting device, and determine whether there is an electrical defect in the array substrate according to the optical information.
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32.发明授权公开(公告)号：US10818798B2
公开(公告)日：2020-10-27
申请号：US16410823
申请日：2019-05-13
Inventor： Yingbin Hu , Ce Zhao , Yuankui Ding , Jun Wang , Jun Liu , Guangyao Li , Yongchao Huang , Wei Li , Liangchen Yan
IPC: H01L29/786 , H01L29/66 , H01L27/12
Abstract: A method for manufacturing a thin film transistor includes forming a light shielding layer and a buffer layer covering the light shielding layer on a substrate. The method includes forming an active layer including a peripheral region and a channel region. The method includes forming a gate insulating layer covering the channel region and forming a contact hole exposing the light shielding layer. The method includes forming a source region and a drain region disposed on both sides of the channel region. The method includes forming an electrode layer including a gate electrode, a source electrode and a drain electrode spaced apart one another. The method includes forming a dielectric layer covering the gate electrode, the source electrode, the drain electrode and the buffer layer.
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公开(公告)号：US20200273939A1
公开(公告)日：2020-08-27
申请号：US16665410
申请日：2019-10-28
Inventor： Haitao Wang , Qinghe Wang , Jun Wang , Guangyao Li , Yang Zhang , Jun Liu , Dongfang Wang
IPC: H01L27/32
Abstract: Disclosed are an array substrate, a method for fabricating the same, a display panel, and a display device, and the array substrate includes: an underlying substrate, and gate lines and data lines located on the underlying substrate, and intersecting with each other, a layer where the gate lines are located is between a layer where the data lines are located, and the underlying substrate; and the array substrate further includes a buffer layer located between the underlying substrate and the layer where the gate lines are located; and the buffer layer includes a plurality of through-holes, where orthographical projections of the through-holes onto the underlying substrate cover orthographical projections of the areas where the gate lines intersect with the data lines, onto the underlying substrate.
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34.发明授权公开(公告)号：US10553801B2
公开(公告)日：2020-02-04
申请号：US15991134
申请日：2018-05-29
Inventor： Jun Wang , Guangyao Li , Dongfang Wang , Jun Liu , Guangcai Yuan , Leilei Cheng
Abstract: The present disclosure relates to a substrate, a method for fabricating the same and an organic light emitting diode display device. The substrate includes a metal foil. A metal material used for the metal foil is capable of being anodized and a plurality of concave light trapping microstructures is formed on a surface of the metal foil.
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公开(公告)号：US20180358583A1
公开(公告)日：2018-12-13
申请号：US15736551
申请日：2017-06-28
Inventor： Zhijie Ye , Yue Hu , Rui Peng , Jun Wang , Kai Xu , Lei Huang , Wenbin Jia , Xinxin Wang
IPC: H01L51/52
CPC classification number: H01L51/5284 , G02B5/3025 , G02B5/3058 , H01L51/5281 , H01L2251/5323
Abstract: A double-sided electroluminescent display panel and a display device are provided. The double-sided electroluminescent display panel includes: a first absorption polarization structure disposed on a first light-emitting surface of a transparent electroluminescent structure, and a first reflective polarization structure disposed on a second light-emitting surface of the transparent EL structure; wherein transmission axes of the first absorption polarization structure and the first reflective polarization structure are perpendicular to each other; the first absorption polarization structure is configured to absorb light of a first wave component and transmit light of a second wave component; the first reflective polarization structure is configured to transmit the light of the first wave component and reflect the light of the second wave component.
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Patent Agency Ranking
公开(公告)号：US20180294289A1
公开(公告)日：2018-10-11
申请号：US15567193
申请日：2016-10-14
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
CPC classification number: H01L27/1244 , G02F1/136259 , G02F2001/136263 , G02F2201/506 , H01L22/22 , H01L27/12 , H01L27/1262
Abstract: The present application discloses an array substrate including a first signal line layer having a plurality of rows of first signal lines; a second signal line layer having a plurality of columns of second signal lines; the plurality of rows of first signal lines crossing over the plurality of columns of second signal lines defining a plurality of subpixels; a first insulating layer and a second insulating layer between the first signal line layer and the second signal line layer; the first insulating layer on a side of the second insulating layer proximal to the first signal line layer; a repair line between the first insulating layer and the second insulating layer, the repair line corresponding to one of the plurality of columns of second signal lines; and a first via and a second via extending through the second insulating layer; the repair line being electrically connected to the corresponding one of the plurality of columns of second signal lines through the first via and the second via, respectively.
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公开(公告)号：US12238973B2
公开(公告)日：2025-02-25
申请号：US17637458
申请日：2021-04-21
Inventor： Jun Wang , Haitao Wang , Tongshang Su , Qinghe Wang , Ning Liu , Bin Zhou , Jun Cheng
IPC: H10K59/122 , H10K59/12 , H10K59/80
Abstract: A display substrate includes a driving circuit layer arranged on a base and a light emitting structure layer arranged on one side, away from the base, of the driving circuit layer; the light emitting structure layer includes an anode, a pixel definition layer, an organic light emitting layer, a cathode, and an auxiliary electrode; the pixel definition layer has a first pixel opening exposing the anode and a second pixel opening exposing the auxiliary electrode; the organic light emitting layer connected to the anode and the cathode connected to the organic light emitting layer are arranged in the first pixel opening; the organic light emitting layer separated from the auxiliary electrode and the cathode located on one side, away from the base, of the organic light emitting layer are arranged in the second pixel opening; and the cathode is connected to the auxiliary electrode in the second pixel opening.
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公开(公告)号：US20240250176A1
公开(公告)日：2024-07-25
申请号：US18613390
申请日：2024-03-22
Inventor： Jun Wang , Zhonghao HUANG
IPC: H01L29/786 , H01L27/12 , H01L29/66
CPC classification number: H01L29/78633 , H01L27/1225 , H01L27/124 , H01L27/127 , H01L27/1288 , H01L29/66969 , H01L29/7869
Abstract: An array substrate, a display device and a fabrication method are provided. The array substrate includes a first metal layer at one side of a base substrate, the first metal layer including a light shielding part, a source, a drain in a display area; a second metal layer at a side, facing away from an active layer, of gate insulating layer, the second metal layer includes a gate, a source-landing electrode a drain-landing electrode in the display area, the source-landing electrode is in contact with the active layer and the source through a first via hole penetrating through the gate insulating layer and a buffer layer and exposing one end of the active layer, the drain-landing electrode is in contact with the active layer and the drain through a second via hole penetrating through the gate insulating layer and the buffer layer and exposing other end of the active layer.
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公开(公告)号：US11631619B2
公开(公告)日：2023-04-18
申请号：US16694831
申请日：2019-11-25
Inventor： Haitao Wang , Guangyao Li , Jun Wang , Qinghe Wang , Dongfang Wang
IPC: H01L21/66 , H01L23/58 , H01L27/12 , H01L29/786 , H01L23/60
Abstract: Embodiments of the present disclosure provide an array substrate comprising a base substrate, a buffer layer disposed on the base substrate, an interlayer dielectric layer disposed on the buffer layer, and a protection layer disposed on the interlayer dielectric layer, where the array substrate further comprises a plurality of first test units and a plurality of test leads. The plurality of test leads are connected to the plurality of first test units in a one-to-one correspondence, and the plurality of test leads are disposed in at least two different layers. A method for manufacturing an array substrate, a display panel, and a display device are further provided.
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公开(公告)号：US11295643B2
公开(公告)日：2022-04-05
申请号：US17032901
申请日：2020-09-25
Inventor： Jun Wang , Dongfang Wang , Guangyao Li , Haitao Wang , Qinghe Wang , Tongshang Su , Chen Shen , Xiaoning Zhang , Youpeng Gan
Abstract: Provided are a detection method and a detection device, the detection method includes: in a first writing stage, providing an active voltage to each data line, each power supply terminal, both ends of a first gate line to-be-detected, an absolute value of the active voltage of each data line is smaller than that of the active voltage of the power supply terminal, an absolute value of the active voltage of the first gate line to-be-detected is smaller than that of the active voltage of each data line; in a first detection stage, maintaining the active voltage of the power supply terminal, providing an inactive voltage to the first gate line to-be-detected and providing an active voltage to the data line, detecting voltages at second electrodes of storage capacitors corresponding to the first gate line to-be-detected, determining whether the first gate line to-be-detected has breakpoint according to the detected voltages.
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