知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

224 records (took 0.025 seconds)

    FLEXIBLE REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) COMPUTATION DEVICE
    33.
    发明申请
    FLEXIBLE REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) COMPUTATION DEVICE 审中-公开

    公开(公告)号：US20190129796A1

    公开(公告)日：2019-05-02

    申请号：US16160782

    申请日：2018-10-15

    Applicant: Amazon Technologies, Inc.

    Inventor： Ron Diamant ,  Nafea Bshara ,  Yaniv Shapira ,  Guy Nakibly

    IPC: G06F11/10 ,  G06F11/20

    Abstract: A method for calculating a plurality (M) of redundancy blocks for multiple (N) data blocks of a plurality (D) of words each, the method comprises: receiving the number (M) of redundancy blocks by a calculator that comprises multiple (R) calculation units; configuring the calculator according to M and R; concurrently calculating, if M equals R, by the multiple (R) calculation units of the calculator, R sets of parity vectors, each set includes a plurality (D) of parity vectors; and calculating the plurality (M) of the redundancy blocks based on the R sets of parity vectors.

    Security testing using a computer add-in card
    34.
    发明授权
    Security testing using a computer add-in card 有权

    公开(公告)号：US10255151B1

    公开(公告)日：2019-04-09

    申请号：US15384031

    申请日：2016-12-19

    Applicant: Amazon Technologies, Inc.

    Inventor： Alex Levin ,  Christopher James BeSerra ,  Ron Diamant

    IPC: G06F11/22 ,  G06F11/30

    Abstract: A smart add-in card can be leveraged to perform testing on a host server computer. The add-in card can include an embedded processor and memory. Tests can be downloaded to the add-in card to test a protocol under which the add-in card operates. In a particular example, a PCIe communication bus couples the motherboard to the add-in card and the tests can purposely violate the PCIe specification. The tests can be developed to test conditions that are typically difficult to test without the use of special hardware. However, the smart add-in card can be a simple Network Interface Card (NIC) that resides on the host server computer during normal operation and is used for communication other than security testing. By using the NIC as a testing device, repeatable and reliable testing can be obtained.

    Hardware security accelerator
    35.
    发明授权
    Hardware security accelerator 有权

    公开(公告)号：US10212138B1

    公开(公告)日：2019-02-19

    申请号：US14980664

    申请日：2015-12-28

    Applicant: AMAZON TECHNOLOGIES, INC.

    Inventor： Ron Diamant ,  Nafea Bshara ,  Leah Shalev ,  Erez Izenberg

    IPC: H04L29/08 ,  H04L29/06 ,  H04L9/14

    Abstract: A hardware security accelerator includes a configurable parser that is configured to receive a packet and to extract from the packet headers associated with a set of protocols. The security accelerator also includes a packet type detection unit to determine a type of the packet in response to the set of protocols and to generate a packet type identifier indicative of the type of the packet. A configurable security unit includes a configuration unit and a configurable security engine. The configuration unit configures the configurable security engine according to the type of the packet and to content of at least one of the headers extracted from the packet. The configurable security engine performs security processing of the packet to provide at least one security result.

    Reducing input/output latency using a direct memory access (DMA) engine
    36.
    发明授权
    Reducing input/output latency using a direct memory access (DMA) engine 有权

    公开(公告)号：US09959227B1

    公开(公告)日：2018-05-01

    申请号：US14971759

    申请日：2015-12-16

    Applicant: Amazon Technologies, Inc.

    Inventor： Ron Diamant ,  Georgy Machulsky ,  Adi Habusha

    IPC: G06F13/00 ,  G06F13/28 ,  G06F12/0862

    CPC classification number: G06F13/28 ,  G06F12/0862 ,  G06F2212/6028

    Abstract: Apparatus and methods are disclosed herein for reducing I/O latency when accessing data using a direct memory access (DMA) engine with a parser. A DMA descriptor indicating memory buffer location can be stored in cache. A DMA descriptor read command is generated and can include a prefetch command. A descriptor with the indicator can be communicated to the DMA engine in response to the read. A second parser can detect the descriptor communication, parse the descriptor, and can prefetch data from memory to cache while the descriptor is being communicated to the DMA engine and/or parsed by the DMA engine parser. When the DMA engine parses the descriptor, data can be accessed from cache rather than memory, to decrease latency.

    Configurable ring oscillator
    37.
    发明授权
    Configurable ring oscillator 有权

    公开(公告)号：US09858042B1

    公开(公告)日：2018-01-02

    申请号：US15274585

    申请日：2016-09-23

    Applicant: AMAZON TECHNOLOGIES, INC.

    Inventor： Ron Diamant

    IPC: G06F7/58 ,  H03K3/03

    CPC classification number: G06F7/588 ,  H03K3/0315

    Abstract: A device includes configurable parallel connected ring oscillators and a finite state machine coupled to the ring oscillators. The finite state machine is configured to cause each of the ring oscillators to operate in an accumulate entropy state for a first period of time and a break phase lock state for a second period of time. When operating in the accumulate entropy state, all of the ring oscillators are in the same configuration. When operating in the break phase lock state, each ring oscillator is in a different configuration than the other ring oscillators.

    Huffman code generation
    38.
    发明授权
    Huffman code generation 有权

    公开(公告)号：US09698819B1

    公开(公告)日：2017-07-04

    申请号：US15390304

    申请日：2016-12-23

    Applicant: AMAZON TECHNOLOGIES, INC.

    Inventor： Michael Baranchik ,  Ron Diamant ,  Muhannad Ghanem ,  Ori Weber

    IPC: H03M7/40 ,  H03M7/30 ,  H03M7/42

    CPC classification number: H03M7/40 ,  H03M7/30 ,  H03M7/405 ,  H03M7/42 ,  H03M7/6076

    Abstract: A method for generating Huffman codewords to encode a dataset includes selecting a Huffman tree type from a plurality of different Huffman tree types. Each of the Huffman tree types specifies a different range of codeword length in a Huffman tree. A Huffman tree of the selected type is produced by: determining a number of nodes available to be allocated as leaves in each level of the Huffman tree accounting for allocation of leaves in each level of the Huffman tree; allocating nodes to be leaves such that the number of nodes allocated in a given level of the Huffman tree is constrained to be no more than the number of nodes available to be allocated in the given level; and assigning the leaves to symbols of the dataset based an assignment strategy selected from a plurality of assignment strategies to produce symbol codeword information.

    Configurable vector compute engine
    40.
    发明授权
    Configurable vector compute engine 有权

    公开(公告)号：US12242853B1

    公开(公告)日：2025-03-04

    申请号：US17937335

    申请日：2022-09-30

    Applicant: Amazon Technologies, Inc.

    Inventor： Paul Gilbert Meyer ,  Ron Diamant ,  Sundeep Amirineni

    IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

    Abstract: A compute channel having a compute pipeline of compute stages can be configured using a configuration pipeline with a control table and a datapath table. The control table stores control entries corresponding to respective microoperations, and each control entry includes control information for the compute channel. A datapath table stores datapath configuration entries corresponding to respective microoperations, and each datapath configuration entry has a datapath configuration that includes computational circuit block configurations to configure respective computational circuit blocks in the compute pipeline of the compute channel. Control logic can issue a microoperation to the compute channel by configuring the compute channel according to the control information of the microoperation obtained from the control table, and by inputting the datapath configuration of the microoperation obtained from the datapath table into the configuration pipeline of the compute channel.

Patent Agency Ranking