Congestion sensitive path-balancing
    31.
    发明授权
    Congestion sensitive path-balancing 有权
    拥塞敏感路径平衡

    公开(公告)号:US09509616B1

    公开(公告)日:2016-11-29

    申请号:US14552373

    申请日:2014-11-24

    CPC classification number: H04L47/125 H04L12/4633 H04L47/11 H04L47/20

    Abstract: Encapsulated packets may be generated for different packets transmitted between a source instance and destination instance in a computer system. The source instance and destination instance may be implemented by different physical hosts linked by multiple network paths. Congestion of the multiple network paths may be determined and path-balancing polices may be implemented in response to the determined congestion. Each encapsulation packet comprises contents of a corresponding packet, and one or more data values selected in accordance with a path-balancing policy. The data values added to one encapsulation packet may differ from those added to another. Different network paths to the destination may be selected for different encapsulation packets of a given transmission based at least in part on the added data values.

    Abstract translation: 可以为在计算机系统中的源实例和目的地实例之间传输的不同数据包生成封装的数据包。 源实例和目的实例可以由通过多个网络路径链接的不同物理主机来实现。 可以确定多个网络路径的拥塞,并且可以响应于所确定的拥塞来实现路径平衡策略。 每个封装分组包括相应分组的内容,以及根据路径平衡策略选择的一个或多个数据值。 添加到一个封装数据包的数据值可能与添加到另一封装数据包的数据值不同。 至少部分地基于所添加的数据值,可以为给定传输的不同封装分组选择到目的地的不同网络路径。

    Networked programmable logic service provider

    公开(公告)号:US11863406B2

    公开(公告)日:2024-01-02

    申请号:US17466944

    申请日:2021-09-03

    CPC classification number: H04L41/5054 G06F9/50 G06F15/7871 H04L41/5096

    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a networked server environment. In one example, a system hosting a network service providing field programmable gate array (FPGA) services includes a network service provider configured to receive a request to implement application logic in a plurality of FPGAs, allocate a computing instance comprising the FPGAs in responses to receiving the request, produce configuration information for programming the FPGAs, and send the configuration information to an allocated computing instance. The system further includes a computing host that is allocated by the network service provider as a computing instance which includes memory, processors configured to execute computer-executable instructions stored in the memory, and the programmed FPGAs.

    Peer-to-peer PCI topology
    35.
    发明授权

    公开(公告)号:US11042496B1

    公开(公告)日:2021-06-22

    申请号:US15282487

    申请日:2016-09-30

    Abstract: Provided are systems and methods for enabling peer-to-peer communications between peripheral devices. In various implementations, a computing system can include a PCI switch device. The first PCI switch device can include a first port and be communicatively coupled to a first root complex port. The first PCI switch device can have access to a first PCI endpoint address range. The computing system can further include a second PCI switch device. The second PCI switch device can include a second port, connected to the first port. The second PCI switch device can be communicatively coupled to a second root complex port that is different from the first root complex port. The second PCI switch device can receive a transaction addressed to the first PCI endpoint address range, and identify the transaction as associated with the second port. The second PCI switch device can subsequently transmit the transaction using the second port.

    Controlling access by a network interface

    公开(公告)号:US10996969B1

    公开(公告)日:2021-05-04

    申请号:US15825068

    申请日:2017-11-28

    Abstract: A server computer toggles between a protected mode and an unprotected mode. In the protected mode, users are unable to access configuration information due to a Base Address Register (BAR) being cleared. However, a service provider can access a Trusted Platform Module (TPM) through an Application Program Interface (API) request. In an unprotected mode, the BAR is programmed so that users can access the configuration information, but the TPM is blocked. Blocking of the TPM is achieved by changing a configuration file, which changes an overall image of the card. With the modified image not matching an original image, the TPM blocks access to data, such as encryption keys. Separate interfaces can be used for user access (PCIe) and service provider access (Ethernet) to the server computer. The server computer can then be toggled back to the protected mode by switching the configuration file to the original configuration file.

    EXTENSION RESOURCE GROUPS OF PROVIDER NETWORK SERVICES

    公开(公告)号:US20210058301A1

    公开(公告)日:2021-02-25

    申请号:US17091811

    申请日:2020-11-06

    Abstract: At a network manager of an extension resource group of a provider network, a message comprising a command to launch a compute instance is received at an address which is part of a first network configured at a premise external to the provider network. The extension resource group includes a first host at the external premise. Within a second network configured at the external premise, the first host is assigned an address within a second address range. Addresses within the second range are also assigned to hosts within the provider network. The command is transmitted to the first host, and a compute instance is instantiated.

    Secure firmware deployment
    39.
    发明授权

    公开(公告)号:US10860305B1

    公开(公告)日:2020-12-08

    申请号:US15721307

    申请日:2017-09-29

    Abstract: A server includes a motherboard and a programmable logic device coupled to the motherboard. The server also includes a hardware device coupled to the motherboard and the programmable logic device. The server further includes a non-volatile memory storing firmware for the hardware device. The non-volatile memory is coupled to the motherboard and the programmable logic device. The server further includes a peripheral device coupled to the motherboard and the programmable logic device. The peripheral device receives firmware data from a management server. The peripheral device verifies that the firmware data corresponds to the hardware device. The peripheral device further holds the hardware device in reset mode. The peripheral device stores the firmware data on the non-volatile memory to update the firmware and releases the hardware device from reset mode after updating the firmware.

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