公开(公告)号：US09983872B2

公开(公告)日：2018-05-29

申请号：US15666978

申请日：2017-08-02

Applicant: ARM Limited

Inventor： Simon John Craske ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30003 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3842

Abstract: An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

公开(公告)号：US20150106585A1

公开(公告)日：2015-04-16

申请号：US14573193

申请日：2014-12-17

Applicant: ARM Limited

Inventor： Nigel John Stephens ,  David James Seal

IPC: G06F9/355 ,  G06F12/10

CPC classification number: G06F9/3557 ,  G06F9/30007 ,  G06F9/30112 ,  G06F9/30167 ,  G06F9/342 ,  G06F9/345 ,  G06F2212/657

Abstract: A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

Abstract translation: 提供了一种数据处理装置，其包括响应于程序指令的处理电路和指令解码器，以控制处理电路执行数据处理。 指令解码器响应于地址计算指令来执行地址计算操作，用于从非固定参考地址和部分偏移值计算部分地址结果，使得可以从...计算指定信息实体的存储位置的完整地址 所述部分地址结果使用至少一个补充程序指令。 部分偏移值具有大于或等于所述指令大小的位宽，并且被编码在所述地址计算指令的至少一个部分偏移字段内。 还提供了相应的数据处理方法，虚拟机和计算机程序产品。