公开(公告)号：US20170286322A1

公开(公告)日：2017-10-05

申请号：US15271102

申请日：2016-09-20

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/14 ,  G06F21/62

CPC classification number: G06F12/1441 ,  G06F12/1081 ,  G06F2212/1052

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

公开(公告)号：US20160364350A1

公开(公告)日：2016-12-15

申请号：US15011291

申请日：2016-01-29

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Vladislav Petkov ,  Radha Kumar Pulyala ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/28 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

Abstract translation: 在处理器间通信（IPC）链路上进行同步多方向传输的方法和装置。 在一个实施例中，同步多向​​传输利用被配置为在第一状态期间累积数据的一个或多个缓冲器。 一个或多个缓冲器还被配置为在第二状态期间传送累积的数据。 在一个或多个处理器不活动的低功率状态期间，数据被累积，并且数据传输在处理器处于活动状态的操作状态期间发生。 此外，在一些变型中，可以对当前可用的传输资源执行数据传输，并且停止直到额外的传输资源可用。 在其他变型中，一个或多个可独立操作的处理器可以执行流量监控过程，以便优化IPC链路的数据吞吐量。