公开(公告)号：US20210272928A1

公开(公告)日：2021-09-02

申请号：US17319558

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Kuan-Liang Liu ,  Kuo Liang Lu ,  Ping-Yin Liu

IPC: H01L23/00 ,  B23K37/04 ,  H01L21/683 ,  H01L21/67 ,  H01L21/20 ,  H01L21/762

Abstract: The present disclosure, in some embodiments, relates to a workpiece bonding apparatus. The workpieces bonding apparatus includes a first substrate holder having a first surface configured to receive a first workpiece, and a second substrate holder having a second surface configured to receive a second workpiece. A vacuum apparatus is positioned between the first substrate holder and the second substrate holder and is configured to selectively induce a vacuum between the first surface and the second surface. The vacuum is configured to attract the first surface and the second surface toward one another.

公开(公告)号：US20210098281A1

公开(公告)日：2021-04-01

申请号：US16812533

申请日：2020-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Kuan-Liang Liu

IPC: H01L21/762 ,  H01L21/84 ,  H01L27/12

Abstract: The present disclosure, in some embodiments, relates to a method of forming a semiconductor structure. The method includes forming a plurality of bulk micro defects within a handle substrate. Sizes of the plurality of bulk micro defects are increased to form a plurality of bulk macro defects (BMDs) within the handle substrate. Some of the plurality of BMDs are removed from within a first denuded region and a second denuded region arranged along opposing surfaces of the handle substrate. An insulating layer is formed onto the handle substrate. A device layer comprising a semiconductor material is formed onto the insulating layer. The first denuded region and the second denuded region vertically surround a central region of the handle substrate that has a higher concentration of the plurality of BMDs than both the first denuded region and the second denuded region.

公开(公告)号：US20200051950A1

公开(公告)日：2020-02-13

申请号：US16654377

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Kuan-Liang Liu ,  Kuo Liang Lu ,  Ping-Yin Liu

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/67 ,  H01L21/20 ,  H01L21/762 ,  B23K37/04

Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.

公开(公告)号：US20190109125A1

公开(公告)日：2019-04-11

申请号：US16201113

申请日：2018-11-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Kuan-Liang Liu ,  Wen-De Wang ,  Yung-Lung Lin

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/58 ,  H01L23/31 ,  H01L25/18 ,  H01L25/065

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.