-
公开(公告)号：US11630797B2
公开(公告)日：2023-04-18
申请号：US17341089
申请日：2021-06-07
Applicant: Texas Instruments Incorporated
Inventor： Anant Shankar Kamath , Rakesh Hariharan , Vivekkumar Ramanlal Vadodariya , Soumi Paul , Mayank Garg
IPC: G06F13/42 , G06F1/3215 , G06F13/38
Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.
-
公开(公告)号：US11563462B1
公开(公告)日：2023-01-24
申请号：US17382499
申请日：2021-07-22
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Mayank Garg , Anant Shankar Kamath
Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
-
公开(公告)号：US10027295B2
公开(公告)日：2018-07-17
申请号：US15142134
申请日：2016-04-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Wenxiao Tan , Mayank Garg , Noble Narku-Tetteh
Abstract: An electrical device (e.g., an integrated circuit) includes an amplifier, a configurable common mode gain trim circuit, and a memory. The configurable common mode gain trim circuit is coupled to the amplifier. The memory is configured to include trim data that is usable during an initialization process for the electrical device to configure the impedance matching circuit.
-
公开(公告)号：US09520822B2
公开(公告)日：2016-12-13
申请号：US13871191
申请日：2013-04-26
Applicant: Texas Instruments Incorporated
Inventor： David Hernandez , Mayank Garg , David J. Baldwin , Brandon James Beckham
CPC classification number: H02P25/032 , H02P6/182
Abstract: Circuits and methods for driving ERM motors are disclosed herein. An embodiment of the circuit includes an input, wherein an input signal is receivable at the input and a back EMF signal. The circuit operates in a closed loop mode when the back EMF signal is less than a lower threshold value and the difference between the value of the input signal and the back EMF signal indicates that the velocity of the motor needs to increase. The circuit operates in an open loop mode when the back EMF signal is greater than a high threshold value and the difference between the value of the input signal and the back EMF signal indicates that the velocity of the motor needs to increase.
Abstract translation: 本文公开了用于驱动ERM电动机的电路和方法。 电路的实施例包括输入，其中输入信号可在输入端接收，反馈EMF信号。 当反电动势信号小于下限阈值时，电路工作在闭环模式，而输入信号与反电动势信号之间的差异表示电动机的速度需要增加。 当反电动势信号大于高阈值时，电路工作在开环模式，输入信号和反电动势信号之间的差值表示电动机的速度需要增加。
-
25.发明申请METHOD AND APPARATUS TO DRIVE A LINEAR RESONANT ACTUATOR AT ITS RESONANT FREQUENCY 审中-公开在谐振频率下驱动线性谐振致动器的方法和装置公开(公告)号：US20150280621A1
公开(公告)日：2015-10-01
申请号：US14733384
申请日：2015-06-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mayank Garg , David Hernandez , Brandon J. Beckham , David J. Baldwin , Brett E. Forejt
CPC classification number: H02P6/006 , G06F3/016 , G06F3/0416 , H02P6/182 , H02P7/00 , H02P7/025 , H02P25/02 , H02P25/032
Abstract: A method for driving a Linear Resonant Actuator (LRA) is provided. During a first off interval, the back-emf of the LRA is measured. During a first off interval, a timer is started when the back-emf reaches a predetermined threshold, and after a predetermined delay has lapsed following the back-emf reaching the predetermined threshold during the first off interval, the LRA is driven over a drive interval having a length and drive strength. A second off interval is entered following the drive interval, and during the second off interval, the back-emf of the LRA is measured. During the second off interval, the timer is stopped when the back-emf reaches the predetermined threshold. The value from the timer that corresponds to the duration between the back-emf reaching the predetermined threshold during the first off interval and the back-emf reaching the predetermined threshold during the second off interval determines the length.
Abstract translation: 提供了一种用于驱动线性谐振致动器（LRA）的方法。 在第一个关闭间隔期间，测量LRA的反电动势。 在第一关闭间隔期间，当反电动势达到预定阈值时，启动定时器，并且在第一关闭间隔期间在反电动势达到预定阈值之后经过预定延迟之后，LRA在驱动间隔 具有长度和驱动力。 在驱动间隔之后输入第二个关闭间隔，并且在第二个关闭间隔期间，测量LRA的反电动势。 在第二关闭间隔期间，当反电动势达到预定阈值时，定时器停止。 对应于在第一关闭间隔期间达到预定阈值的反电动势之间的持续时间的定时器的值和在第二关闭间隔期间达到预定阈值的反电动势确定长度。
-
Patent Agency Ranking
公开(公告)号：US11984941B2
公开(公告)日：2024-05-14
申请号：US18100131
申请日：2023-01-23
Applicant: Texas Instruments Incorporated
Inventor： Srijan Rastogi , Mayank Garg , Anant Shankar Kamath
CPC classification number: H04B3/36 , H03F3/45179
Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
-
公开(公告)号：US11556492B1
公开(公告)日：2023-01-17
申请号：US17363106
申请日：2021-06-30
Applicant: Texas Instruments Incorporated
Inventor： Ganapathi Hegde , Krushal Shah , Mayank Garg , Luis Eduardo Ossa , Vashist Bist
IPC: G06F13/42
Abstract: A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.
-
公开(公告)号：US20220224335A1
公开(公告)日：2022-07-14
申请号：US17700045
申请日：2022-03-21
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Win Naing Maung , Bharath Kumar Singareddy , Soumi Paul , Mayank Garg , Suzanne Mary Vining
IPC: H03K19/0185 , H04L7/00 , H04B3/36 , G06F13/42 , H04L25/02
Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.
-
公开(公告)号：US20200328715A1
公开(公告)日：2020-10-15
申请号：US16843962
申请日：2020-04-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Luis Eduardo Ossa , Krushal Shah , Mayank Garg , Hao Wang , Haozhi Liu
Abstract: A system for driving one or more motors includes: a controller having an instruction output; one or more motor drivers, each of the motor drivers are coupled to the instruction output of the controller and each of the motor drivers having a unique address; and wherein each motor driver is only operable to receive instruction from the controller when its unique address is provided by the controller at the instruction output.
-
公开(公告)号：US10700586B2
公开(公告)日：2020-06-30
申请号：US15142852
申请日：2016-04-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shyamsunder Balasubramanian , Toshio Yamanaka , Toru Tanaka , Mayank Garg
IPC: H02P29/02 , H02P6/08 , H03K5/134 , H02P6/12 , H02M1/08 , H02M1/32 , H03K17/12 , H02P29/024 , H03K17/0812 , H03K17/687
Abstract: A gate driver circuit includes a comparator and a gate driver. The comparator is configured to detect a short circuit in a first power field effect transistor (FET). The gate driver is configured to drive a gate of the first power FET by generating a first signal at a first drive current. In response to the comparator detecting a short circuit in the first power FET, the gate driver is further configured to pulse the first signal at a first pulldown current. After the pulse has ended, the gate driver is further configured to drive the gate of the first power FET at a first hold current. The first hold current is less than the first pulldown current.
-
-
-
-
-
-
-
-
-
Search Results
33
records
(took 0.017 seconds)
