公开(公告)号：US20220344264A1

公开(公告)日：2022-10-27

申请号：US17236234

申请日：2021-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L23/535 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

公开(公告)号：US11482447B2

公开(公告)日：2022-10-25

申请号：US16923424

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

公开(公告)号：US11362030B2

公开(公告)日：2022-06-14

申请号：US16887475

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Teng Dai ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Hsi-Wen Tien ,  Wei-Hao Liao

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive via is disposed within the first ILD layer. A plurality of conductive wires overlie the first ILD layer. A second ILD layer is disposed laterally between the conductive wires, where the second ILD layer comprises a first material. A sidewall spacer structure is disposed between the second ILD layer and the plurality of conductive wires. The sidewall spacer structure continuously extends along opposing sidewalls of each conductive wire. A top surface of the sidewall spacer structure is vertically above a top surface of the plurality of conductive wires, and the sidewall spacer structure comprises a second material different from the first material.

公开(公告)号：US20210391261A1

公开(公告)日：2021-12-16

申请号：US16898705

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao Liao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.

公开(公告)号：US11063213B2

公开(公告)日：2021-07-13

申请号：US16664815

申请日：2019-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  David Dai ,  Chung-Ju Lee

IPC: H01L47/00 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L27/24 ,  H01L43/08

Abstract: A method includes depositing a bottom electrode layer, a resistance switching element layer, and a top electrode layer over a first dielectric layer; etching the top electrode layer and the resistance switching element layer to form a resistance switching element over the bottom electrode layer and a top electrode over the resistance switching element; depositing a metal-containing compound layer over the top electrode, the resistance switching element, and the bottom electrode layer; and etching the metal-containing compound layer and the bottom electrode layer to form a bottom electrode over the first dielectric layer.

公开(公告)号：US10700264B2

公开(公告)日：2020-06-30

申请号：US16511862

申请日：2019-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Liao ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A method includes forming in sequence a bottom magnetic layer, a tunnel barrier layer, a top magnetic layer, and a top electrode layer over a bottom electrode layer; performing a first etching process to recess the top electrode layer, in which the first etching process stops before the top magnetic layer is etched; performing a second etching process to pattern the top electrode layer as a top electrode and the top magnetic layer as a patterned top magnetic layer, in which the second etching process stops before the bottom magnetic layer is etched; forming a first spacer around the top electrode and the patterned top magnetic layer; and after forming the first spacer, performing a third etching process to pattern the tunnel barrier layer as a patterned tunnel barrier layer and the bottom magnetic layer as a patterned bottom magnetic layer.

公开(公告)号：US20200098978A1

公开(公告)日：2020-03-26

申请号：US16510296

申请日：2019-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Hao Liao ,  Hsi-Wen Tien ,  Chih-Wei Lu ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: A magnetic memory device includes a bottom electrode, a magnetic tunneling junction disposed over the bottom electrode, and a top electrode disposed over the magnetic tunneling junction, wherein the top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer, and wherein the second top electrode layer is thicker than the first top electrode layer.

公开(公告)号：US10461246B2

公开(公告)日：2019-10-29

申请号：US15706709

申请日：2017-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  David Dai ,  Chung-Ju Lee

IPC: H01L47/00 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L43/02 ,  H01L27/24 ,  H01L43/08

Abstract: A method for manufacturing a memory device is provided. The method includes forming a stack over a first portion of a bottom electrode layer, in which the stack comprises a resistance switching element and a top electrode over the resistance switching element; forming a first spacer around the resistance switching element; forming a penetration barrier layer around the resistance switching element; and removing a second portion of the bottom electrode layer using an etch operation, in which the penetration barrier layer has higher resistance to penetration of an etchant used in the etch operation than that of the first spacer.

公开(公告)号：US10355198B2

公开(公告)日：2019-07-16

申请号：US15811405

申请日：2017-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao Liao ,  Chih-Wei Lu ,  Hsi-Wen Tien ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A memory device includes an MTJ structure and a first metal residue. The MTJ structure includes a top surface having a first width, a bottom surface having a second width greater than the first width, and a stepped sidewall structure between the top surface and the bottom surface. The stepped sidewall structure includes a first sidewall, a second sidewall, and an intermediary surface connecting the first sidewall to the second sidewall. The first metal residue is in contact with the first sidewall and not in contact with the second sidewall.

公开(公告)号：US10270028B1

公开(公告)日：2019-04-23

申请号：US15813055

申请日：2017-11-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsi-Wen Tien ,  Chih-Wei Lu ,  Wei-Hao Liao ,  Pin-Ren Dai ,  Chung-Ju Lee

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22

Abstract: A method for manufacturing a memory device, the method includes forming an opening in a dielectric layer; overfilling the opening with a bottom electrode layer; removing a first portion of the bottom electrode layer outside the opening, while leaving a second portion of the bottom electrode layer in the opening to form a bottom electrode; and forming a stack over the bottom electrode, the stack comprising a resistance switching element in contact with the bottom electrode and a top electrode over the resistance switching element.